Senior / Staff Engineer - Digital Design

INFINEON TECHNOLOGIES ASIA PACIFIC PTE LTD; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

INFINEON TECHNOLOGIES ASIA PACIFIC PTE LTD in Singapore seeks a hardware engineer to drive RTL-to-gate synthesis and STA, using Synopsys Design Compiler, Fusion Compiler, Cadence Genus, PrimeTime and Tempus. You will collaborate with design, verification and PD teams to achieve timing closure, optimize timing, power and area, and develop automation scripts in Python, Tcl and Perl.

The role requires 3–5+ years in hardware engineering and a Bachelor’s/Master’s in Electrical or Computer

Qualifications

• Bachelor’s or Master’s in Electrical or Computer Engineering or related field.
• 3–5+ years of hardware engineering experience.
• Hands-on experience with logic synthesis, LEC, STA, timing constraints, and timing convergence.
• Background in physical design and optimization (placement/routing/cell sizing) to improve timing and power.

Responsibilities

• Perform RTL-to-gate synthesis using EDA tools to generate optimized gate-level netlists.
• Run STA and timing checks across pre- and post-layout stages with PrimeTime/Tempus.
• Collaborate with design, verification, and PD teams to achieve timing closure and optimization.
• Assist in developing and maintaining synthesis and STA scripts and methodologies.
• Analyze and resolve timing issues with cross-functional teams.
• Run timing constraint checks and LEC.
• Participate in design reviews and report findings and recommendations.
• Document synthesis and STA results clearly.

Skills

Scripting

Communication

Team collaboration

Hardware engineering

Education

Bachelor's/Master's in Electrical Engineering or Computer Engineering

Tools

Synopsys Design Compiler

Fusion Compiler

Cadence Genus

Synopsys PrimeTime

Cadence Tempus

ICC2

Innovus

Job description

Your role
Key responsibilities in your new role

• Perform RTL-to-gate synthesis using EDA tools such as Synopsys Design Compiler/Fusion Compiler or Cadence Genus to generate optimized gate-level netlists.
• Run Static Timing Analysis (STA) including setup/hold checks across pre- and post-layout stages using tools such as Synopsys PrimeTime or Cadence Tempus.
• Collaborate with design, verification, and PD teams to ensure timing closure and design optimization.
• Assist in the development and maintenance of synthesis and STA scripts and methodologies.
• Analyze and resolve timing issues, working closely with cross-functional teams.
• Run timing constraint checks and logic equivalency checks (LEC).
• Participate in design reviews and provide feedback on timing and synthesis aspects.
• Document and report synthesis and STA results, highlighting key findings and recommendations.

Your profile
Qualifications and skills to help you succeed

• Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 3–5+ years of hardware engineering (or related) experience.
• Hands-on experience with logic synthesis, LEC, STA, timing constraints, and timing convergence.
• Expertise in timing closure via ECOs, including crosstalk and noise analysis.
• Background in physical design and optimization (e.g., placement, routing, cell sizing) to improve timing and power.
• Ability to run basic PD steps such as floorplanning and placement using ICC2 or Innovus (plus).
• Proficiency in scripting (Python, Tcl, Perl) for automation.
• Excellent verbal and written communication skills.