Senior Staff Digital Design Engineer

Darwin Recruitment; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Darwin Recruitment represents an innovative semiconductor company seeking a Staff / Senior Staff Digital IC Design Engineer in Singapore. The role focuses on architecture, design, optimisation and validation of high-performance digital ICs, collaborating with cross-functional teams to deliver advanced CMOS solutions for quantum computing.

You will work on RTL architectures, synthesis-ready RTL, STA, DFT, and tapeout processes, contributing to complex digital designs from concept to silicon.

Qualifications

• Master’s or PhD in Electrical Engineering or related field.
• 3–5+ years of experience in digital IC design.
• Experience from architecture through silicon tapeout.
• Strong RTL design experience with Verilog/SystemVerilog.
• Knowledge of DFT, STA and PPA optimisation.

Responsibilities

• Develop RTL architectures and translate specs into hardware designs.
• Implement synthesis-ready RTL using Verilog/SystemVerilog.
• Perform logic synthesis and optimise for Power, Performance and Area.
• Conduct Static Timing Analysis and fix timing violations.
• Implement Design for Testability, including scan and BIST.
• Collaborate with verification, physical design and DFT teams.
• Support prototyping, validation and tapeout activities.
• Translate requirements into practical semiconductor solutions.

Skills

RTL design

Verilog/SystemVerilog

PPA optimisation

STA

DFT

Tapeout

PCIe/AXI/NoC

NoC

Education

Master’s or PhD in Electrical Engineering

Job description

Staff / Senior Staff Digital IC Design Engineer

An innovative technology company operating in the advanced semiconductor and quantum computing industry is developing next-generation CMOS control and readout solutions to address the scalability and performance challenges of quantum computing.

The company is looking for an experienced Staff / Senior Staff Digital IC Design Engineer to join its engineering team. You will contribute to the architecture, design, optimisation and validation of complex digital ICs, working closely with cross-functional engineering teams and external stakeholders to deliver high-performance semiconductor solutions.

Key Responsibilities

• Develop RTL architectures and translate high-level chip specifications into functional hardware designs.

• Implement synthesis-ready RTL using Verilog/SystemVerilog or other HDLs.

• Perform logic synthesis and optimise designs for Power, Performance and Area (PPA).

• Conduct Static Timing Analysis (STA) and resolve setup and hold timing violations.

• Implement Design for Testability (DFT), including scan chains and Built-In Self-Test (BIST).

• Collaborate with verification, physical design and DFT teams to resolve design challenges.

• Support prototyping, validation and silicon tapeout activities.

• Work with internal and external stakeholders to translate technical requirements into practical solutions.

Requirements

• Master’s or PhD in Electrical Engineering, Computer Engineering or a related discipline.

• 3-5+ years of industry experience in digital IC design.

• Proven experience taking complex digital designs from architecture through to silicon tapeout.

• Strong RTL design experience using Verilog/SystemVerilog.

• Experience with logic synthesis, PPA optimisation and Static Timing Analysis (STA).

• Knowledge of Design for Testability (DFT), including scan insertion and BIST.

• Strong understanding of high-speed communication protocols such as PCIe, CXL or USB4, or high-performance bus architectures such as AMBA AXI/CHI and Network-on-Chip (NoC).

• Experience collaborating with verification and physical design teams.