Sr/ IC Design Engineer (Physical Design)

Ethos Search Associates Pte Ltd; Singapore; On-site; SGD 60,000 - 80,000; Full time

Job summary

Ethos Search Associates Pte Ltd is looking for an engineer to design and develop ICs using leading EDA software. Responsibilities include GDS validation and maintaining synthesis and Static Timing Analysis. The ideal candidate holds a degree in Electronics or related field and has at least one year of experience in the design process. Proficiency in EDA tools like Synopsys ICC2, Perl, and TCL is required. Good communication skills and teamwork are essential for this role.

Qualifications

• 1+ years of experience in design flow from Netlist to GDS.
• Good experience in synthesis, layout, and timing closure sign-off.
• Knowledge of backend verification and deep sub-micron routing.

Responsibilities

• Design and develop ICs using EDA software.
• Responsible for GDS validation like DRC/LVS and timing closure.
• Maintain synthesis, DFT and Static Timing Analysis.

Skills

Design flow from Netlist to GDS

Static timing analysis

EDA tools (Synopsys ICC2)

Perl

TCL

Education

Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering

Tools

EDA software

Job description

Job De ion

• Design and Develop ICs using leading EDA software; work on RTL to GDS, including synthesis, layout, floor planning, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis s using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

Job Requirements

• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with 1 year or more experience
• Good experience and knowledge in design flow from Netlist to GDS, Synthesis, layout, Floor Planning, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills