Senior Digital Logic Engineer - 3D-NAND RTL Architect

Brightecs Innovation Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Brightecs Innovation Pte. Ltd. is seeking a senior IC design engineer to architect and verify digital control logic for 3D-NAND memory. You will implement RTL encoding in Verilog/SystemVerilog, design FSMs, and ensure JEDEC-compliant interfaces.

You will collaborate with FW, analog/mixed-signal, and verification teams, contribute to UVM environments, DFT, FPGA prototyping, and post-silicon debugging to optimize performance and power.

Qualifications

• Education: Master's degree or above.
• Major: Microelectronics and Integrated Circuits, Electrical Engineering, Computer Engineering, or related fields.
• Experience: Minimum 5 years digital IC design; NAND Flash/SSD controller exposure is a plus.
• Familiar with ONFI 4.x or Toggle 2.0/3.0 protocols; practical interface IP development/integration.
• Experience with 3D-NAND/TLC/QLC architectures and ECC interfaces.

Responsibilities

• Architect and verify digital control logic for 3D-NAND memory.
• Design RTL encoding, FSMs, and a compliant command/address/parameter parsing path.
• Develop timing control logic for internal signals (tR, tPROG, tBERS).
• Collaborate with FW/-system teams on register maps, interrupts, and debug interfaces.
• Support UVM verification, DFT, FPGA prototyping, tape-out, and post-silicon debugging.

Skills

RTL encoding

FSM design

Verilog/SystemVerilog

Timing control

ONFI/Toggle protocol

ECC interface

UVM verification

DFT support

FPGA prototyping

Education

Master's degree in Microelectronics/ICs

Tools

FPGA prototyping

UVM

Job description

Brightecs Innovation Pte. Ltd. is seeking a senior IC design engineer to architect and verify digital control logic for 3D-NAND memory. You will implement RTL encoding in Verilog/SystemVerilog, design FSMs, and ensure JEDEC-compliant interfaces.

You will collaborate with FW, analog/mixed-signal, and verification teams, contribute to UVM environments, DFT, FPGA prototyping, and post-silicon debugging to optimize performance and power.