Senior Digital IC Design Engineer — RTL to Silicon

Darwin Recruitment

Singapore

On-site

SGD 120,000 - 180,000

Full time

42 hours ago
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Job summary

Darwin Recruitment represents an innovative semiconductor company seeking a Staff / Senior Staff Digital IC Design Engineer in Singapore. The role focuses on architecture, design, optimisation and validation of high-performance digital ICs, collaborating with cross-functional teams to deliver advanced CMOS solutions for quantum computing.

You will work on RTL architectures, synthesis-ready RTL, STA, DFT, and tapeout processes, contributing to complex digital designs from concept to silicon.

Qualifications

  • Master’s or PhD in Electrical Engineering or related field.
  • 3–5+ years of experience in digital IC design.
  • Experience from architecture through silicon tapeout.
  • Strong RTL design experience with Verilog/SystemVerilog.
  • Knowledge of DFT, STA and PPA optimisation.

Responsibilities

  • Develop RTL architectures and translate specs into hardware designs.
  • Implement synthesis-ready RTL using Verilog/SystemVerilog.
  • Perform logic synthesis and optimise for Power, Performance and Area.
  • Conduct Static Timing Analysis and fix timing violations.
  • Implement Design for Testability, including scan and BIST.
  • Collaborate with verification, physical design and DFT teams.
  • Support prototyping, validation and tapeout activities.
  • Translate requirements into practical semiconductor solutions.

Skills

RTL design
Verilog/SystemVerilog
PPA optimisation
STA
DFT
Tapeout
PCIe/AXI/NoC
NoC

Education

Master’s or PhD in Electrical Engineering

Job description

Darwin Recruitment represents an innovative semiconductor company seeking a Staff / Senior Staff Digital IC Design Engineer in Singapore. The role focuses on architecture, design, optimisation and validation of high-performance digital ICs, collaborating with cross-functional teams to deliver advanced CMOS solutions for quantum computing.

You will work on RTL architectures, synthesis-ready RTL, STA, DFT, and tapeout processes, contributing to complex digital designs from concept to silicon.

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