Senior Digital Design Engineer — RTL to Timing Expert

Infineon Technologies AG; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

Infineon Technologies AG in Singapore invites a Digital Design Engineer to join our R&D team to shape the future of technology. You will perform RTL-to-gate synthesis, run STA, collaborate with design, verification and PD to ensure timing closure, and contribute to scripting and methodology development.

The role requires 3–5+ years of hardware experience, strong timing analysis, PD familiarity with ICC2/Innovus, and scripting in Python/Tcl/Perl.

Qualifications

• Bachelor’s or master’s in Electrical/Computer Engineering.
• 3–5+ years hardware engineering experience.
• Hands-on with logic synthesis, LEC, STA, timing constraints.
• Experience with timing closure via ECOs, crosstalk and noise analysis.
• PD background: floorplanning, placement, routing.
• Scripting in Python/Tcl/Perl for automation.
• Strong communication skills.

Responsibilities

• Perform RTL-to-gate synthesis and generate gate-level netlists.
• Run STA and timing checks across pre- and post-layout.
• Collaborate with design, verification and PD teams for timing closure.
• Develop and maintain synthesis and STA scripts.
• Analyze timing issues and report findings.
• Participate in design reviews and provide optimization insights.
• Document results and recommendations.

Skills

Logic synthesis

LEC

STA

Timing constraints

Timing convergence

Scripting

Python

Tcl

Perl

Automation

Placement

Routing

Cell sizing

ICC2

Innovus

Physical design

Education

Bachelor’s/Master’s degree in Electrical Engineering or Computer Engineering

Tools

Synopsys Design Compiler

Fusion Compiler

Cadence Genus

Synopsys PrimeTime

Cadence Tempus

ICC2

Innovus

Job description

Infineon Technologies AG in Singapore invites a Digital Design Engineer to join our R&D team to shape the future of technology. You will perform RTL-to-gate synthesis, run STA, collaborate with design, verification and PD to ensure timing closure, and contribute to scripting and methodology development.

The role requires 3–5+ years of hardware experience, strong timing analysis, PD familiarity with ICC2/Innovus, and scripting in Python/Tcl/Perl.