Senior Digital IC Design Engineer: RTL to Tapeout

IC Resources; Singapore; On-site; SGD 110,000 - 150,000; Full time

Job summary

IC Resources is recruiting for a Senior Digital IC Design Engineer to join its client’s engineering team in Singapore. The role covers the full IC development flow from architecture and RTL through verification, implementation and tapeout, with a focus on delivering high-performance digital silicon.

You will work across RTL design, synthesis, timing closure, DFT and collaboration with verification and physical design teams.

Qualifications

• Master's or PhD in Electrical or Computer Engineering.
• 3 to 5+ years of commercial digital IC design.
• Experience taking complex ICs from architecture to tapeout.
• Strong RTL design and HDL knowledge.
• Familiarity with PCIe Gen5/6, CXL, USB4, or AMBA AXI/CHI/NoC.
• Proficient in synthesis, timing closure and PPA optimization.

Responsibilities

• Define RTL architecture and translate specs into digital blocks.
• Develop synthesis-ready RTL and control logic.
• Perform logic synthesis and optimize for power, performance, area.
• Analyse STA results and resolve timing issues.
• Implement DFT features including scan and BIST.
• Collaborate with verification, physical design and DFT teams.
• Support prototyping, validation and deployment.
• Engage with customers and external partners.

Skills

RTL design

HDL languages

Synthesis

Timing closure

PPA optimization

DFT features

Digital IC design

Industry experience

Education

Master's or PhD in Electrical/Computer Engineering

Tools

Synthesis tools

STA tools

PCIe Gen5/6 experience

AMBA AXI/CHI knowledge

Job description

IC Resources is recruiting for a Senior Digital IC Design Engineer to join its client’s engineering team in Singapore. The role covers the full IC development flow from architecture and RTL through verification, implementation and tapeout, with a focus on delivering high-performance digital silicon.

You will work across RTL design, synthesis, timing closure, DFT and collaboration with verification and physical design teams.