Digital Design & Implementation Engineer (RTL to Timing)

GlobalFoundries; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

GlobalFoundries in Singapore is seeking a Digital Design and Implementation Engineer to contribute to RTL development, synthesis, floorplanning, place and route, and timing analysis for test-chip designs.

You will work with industry-standard tools like VCS, ICC2, Genus, Innovus, and Virtuoso to push yields and performance in a fast-paced semiconductor environment.

Experience in digital physical design is preferred and a degree in Electrical/Electronic Engineering is required.

Qualifications

• Experience in digital physical design is preferred.
• Degree in Electrical / Electronic Engineering or a related field.

Responsibilities

• Develop DoE blocks for standard cells and memory macros to support yield measurements and characterization.
• Create and modify RTL, iterating parameters for optimal cell utilization within timing constraints.
• Drive the full digital implementation flow: synthesis, floorplan, power mesh, and place & route.
• Run physical verification (DRC, LVS, DFM, MAS) and resolve violations.
• Perform timing extraction and static timing analysis to close timing.
• Execute logical equivalence checks to ensure design integrity.

Skills

Verilog

Python

Ticker coding

Education

Electrical/Electronic Engineering degree

Tools

VCS

ICC2

Genus

Innovus

Virtuoso

Job description

GlobalFoundries in Singapore is seeking a Digital Design and Implementation Engineer to contribute to RTL development, synthesis, floorplanning, place and route, and timing analysis for test-chip designs.

You will work with industry-standard tools like VCS, ICC2, Genus, Innovus, and Virtuoso to push yields and performance in a fast-paced semiconductor environment.

Experience in digital physical design is preferred and a degree in Electrical/Electronic Engineering is required.