Senior DFT Engineer: ASIC Test & Validation Expert

Bitdeer (NASDAQ: BTDR)

Singapore

On-site

SGD 120,000 - 170,000

Full time

14 days+

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Benefits offered by this job

Diversity culture

Open workspaces

Mentorship & training

Job summary

Bitdeer is seeking an experienced test engineer to lead boundary scan and DFT initiatives for its cutting-edge ASIC/SoC projects. You will collaborate with design teams to create robust test plans, implement JTAG solutions, and optimize ATPG and compression methods to ensure high-yield silicon.

The role demands 8+ years in DFT, proficiency with Genus/Design Compiler, and hands-on experience with Tessent. Bitdeer offers an inclusive, fast-growing environment and opportunities to influence the

Qualifications

Requires a Bachelor/Master/PhD in Electrical or Computer Engineering.
Minimum 8 years of relevant experience.
Experience with DFT insertion, timing and congestion resolution with implementation teams.

Responsibilities

Implement and optimize boundary scan, MBIST, test logic insertion, and JTAG solutions.
Develop and validate scan ATPG and compression methodologies.
Conduct DFT and post-gate simulations to ensure design robustness.
Generate and apply DFT constraints for efficient testing.
Deliver test patterns and assist ATE debugging with the test team.
Utilize EDA tools like Tessent to enhance test processes and efficiency.
Provide mentorship and guidance to junior engineers.