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Bitdeer is seeking an experienced test engineer to lead boundary scan and DFT initiatives for its cutting-edge ASIC/SoC projects. You will collaborate with design teams to create robust test plans, implement JTAG solutions, and optimize ATPG and compression methods to ensure high-yield silicon.
The role demands 8+ years in DFT, proficiency with Genus/Design Compiler, and hands-on experience with Tessent. Bitdeer offers an inclusive, fast-growing environment and opportunities to influence the
Bitdeer is seeking an experienced test engineer to lead boundary scan and DFT initiatives for its cutting-edge ASIC/SoC projects. You will collaborate with design teams to create robust test plans, implement JTAG solutions, and optimize ATPG and compression methods to ensure high-yield silicon.
The role demands 8+ years in DFT, proficiency with Genus/Design Compiler, and hands-on experience with Tessent. Bitdeer offers an inclusive, fast-growing environment and opportunities to influence the