Senior DFT Engineer for SoC/ASIC Test & Verification

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 100,000 - 160,000; Full time

Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED is seeking a Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team.

You will implement and verify DFT solutions across complex hierarchical designs, perform scan insertion and test compression, and collaborate with ATE and physical design teams to ensure first-pass silicon success. The role requires hands-on DFT insertion, verification, and strong scripting skills to automate workflows.

Qualifications

• Bachelor's or master's degree in electrical/computer engineering or related field.

Responsibilities

• Develop and implement DFT architectures for hierarchical SoC/ASIC designs.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent architectures.
• Validate SSN topology and balance scan chains across clock domains.
• Integrate boundary scan (IEEE 1149.x) and test access mechanisms for chip-level testability.
• Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults.

Skills

DFT architectures

SSN

ATPG

Verilog

Tessent

Scripting (Python/Perl/TCL)

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Siemens Tessent

Job description

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED is seeking a Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team.

You will implement and verify DFT solutions across complex hierarchical designs, perform scan insertion and test compression, and collaborate with ATE and physical design teams to ensure first-pass silicon success. The role requires hands-on DFT insertion, verification, and strong scripting skills to automate workflows.