DFT engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 55,000 - 90,000; Full time

Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED seeks a Design-for-Test (DFT) Engineer to drive DFT across complex hierarchical SoC/ASIC designs, insert scans, perform compression, and verify DFT effectiveness.

You will collaborate with Physical design and ATE teams to ensure first-pass silicon success and robust test strategy. The role involves hands-on DFT insertion and verification, including ATPG pattern generation and timing validation, with strong scripting in TCL, Python or Perl to

Qualifications

• Experience in DFT design and verification with emphasis on hierarchical designs.
• Hands-on DFT insertion, verification, and pattern generation.
• Familiarity with industry test flows and ATE environments.

Responsibilities

• Develop and implement DFT architectures for hierarchical SoC/ASIC designs.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent.
• Validate SSN topology, scan chain balancing and clock-domain crossings.
• Integrate Boundary Scan and other test access mechanisms.
• Generate ATPG patterns for stuck-at, transition, and path delay faults.
• Perform DFT verification using verilog/gate-level simulations.
• Collaborate with cross-functional teams to resolve timing challenges.
• Prepare and validate timing and pattern files for tester compatibility.

Skills

Scan-based DFT

Test compression

Hierarchical DFT

ATPG generation

Fault coverage

Gate-level DFT verification

TCL scripting

Python scripting

Perl scripting

Automation

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Siemens Tessent

Advantest

Teradyne

Job description

We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team. The successful candidate will be responsible for implementing and verifying DFT solutions across complex hierarchical designs. This position involves hands-on work in DFT insertion, and comprehensive DFT verification to ensure first-pass silicon success. You will collaborate closely with Physical design team, ATE test teams to develop efficient, high-quality test strategies aligned with industry standards.

Key Responsibilities

• a) Develop and implement DFT architectures for hierarchical SoC and ASIC designs, including both block-level and top-level DFT integration.
• b) Perform scan insertion, test point insertion, and test compression using SSN or equivalent compression architectures.
• c) Validate Serial Stream Network (SSN) topology, managing scan chain balancing, clock domain crossings.
• d) Integrate Boundary scan (IEEE 1149.x) and other test access mechanisms for chip-level testability.
• e) Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults to ensure optimal test coverage.
• f) Perform DFT verification, including verilog / gate level simulation
• g) Work closely with cross-functional teams to resolve DFT/testing timing challenges.
• i) Collaborate with ATE engineers to prepare and validate timing and pattern files (STIL/WGL) for tester compatibility and production readiness.
• j) Support silicon bring-up, production test debugging through Diagnostics and failure analysis.

Qualifications

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
• Minimum 1 years of experience in DFT design and verification
• Strong understanding of scan-based test architectures, test compression, and hierarchical DFT implementation.
• Hands-on experience with DFT tools such as Siemens Tessent.
• Proficiency in ATPG generation, fault coverage analysis, and gate-level DFT verification.
• Familiarity with ATE test flows and pattern validation on platforms such as Advantest or Teradyne.
• Strong scripting skills in TCL, Perl, or Python for DFT automation.