Senior / Staff DFT engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 100,000 - 160,000; Full time

Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED is seeking a Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team.

You will implement and verify DFT solutions across complex hierarchical designs, perform scan insertion and test compression, and collaborate with ATE and physical design teams to ensure first-pass silicon success. The role requires hands-on DFT insertion, verification, and strong scripting skills to automate workflows.

Qualifications

• Bachelor's or master's degree in electrical/computer engineering or related field.

Responsibilities

• Develop and implement DFT architectures for hierarchical SoC/ASIC designs.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent architectures.
• Validate SSN topology and balance scan chains across clock domains.
• Integrate boundary scan (IEEE 1149.x) and test access mechanisms for chip-level testability.
• Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults.

Skills

DFT architectures

SSN

ATPG

Verilog

Tessent

Scripting (Python/Perl/TCL)

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Siemens Tessent

Job description

We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team. The successful candidate will be responsible for implementing and verifying DFT solutions across complex hierarchical designs. This position involves hands‑on work in DFT insertion, and comprehensive DFT verification to ensure first‑pass silicon success. You will collaborate closely with Physical design team, ATE test teams to develop efficient, high‑quality test strategies aligned with industry standards.

Key Responsibilities

• a) Develop and implement DFT architectures for hierarchical SoC and ASIC designs, including both block-level and top-level DFT integration.
• b) Perform scan insertion, test point insertion, and test compression using SSN or equivalent compression architectures.
• c) Validate Serial Stream Network (SSN) topology, managing scan chain balancing, clock domain crossings.
• d) Integrate Boundary scan (IEEE 1149.x) and other test access mechanisms for chip‑level testability.
• e) Generate and analyze ATPG patterns for stuck‑at, transition, and path delay faults to ensure optimal test coverage.
• f) Perform DFT verification, including verilog / gate level simulation
• g) Work closely with cross‑functional teams to resolve DFT/testing timing challenges.
• i) Collaborate with ATE engineers to prepare and validate timing and pattern files (STIL/WGL) for tester compatibility and production readiness.
• j) Support silicon bring‑up, production test debugging through Diagnostics and failure analysis.

Qualifications

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
• Minimum 5 years of experience in DFT design and verification
• Strong understanding of scan-based test architectures, test compression, and hierarchical DFT implementation.
• Hands‑on experience with DFT tools such as Siemens Tessent.
• Proficiency in ATPG generation, fault coverage analysis, and gate-level DFT verification.
• Familiarity with ATE test flows and pattern validation on platforms such as Advantest or Teradyne.
• Strong scripting skills in TCL, Perl, or Python for DFT automation.