SoC DFT Engineer: Test Architecture & Verification

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 55,000 - 90,000; Full time

Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED seeks a Design-for-Test (DFT) Engineer to drive DFT across complex hierarchical SoC/ASIC designs, insert scans, perform compression, and verify DFT effectiveness.

You will collaborate with Physical design and ATE teams to ensure first-pass silicon success and robust test strategy. The role involves hands-on DFT insertion and verification, including ATPG pattern generation and timing validation, with strong scripting in TCL, Python or Perl to

Qualifications

• Experience in DFT design and verification with emphasis on hierarchical designs.
• Hands-on DFT insertion, verification, and pattern generation.
• Familiarity with industry test flows and ATE environments.

Responsibilities

• Develop and implement DFT architectures for hierarchical SoC/ASIC designs.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent.
• Validate SSN topology, scan chain balancing and clock-domain crossings.
• Integrate Boundary Scan and other test access mechanisms.
• Generate ATPG patterns for stuck-at, transition, and path delay faults.
• Perform DFT verification using verilog/gate-level simulations.
• Collaborate with cross-functional teams to resolve timing challenges.
• Prepare and validate timing and pattern files for tester compatibility.

Skills

Scan-based DFT

Test compression

Hierarchical DFT

ATPG generation

Fault coverage

Gate-level DFT verification

TCL scripting

Python scripting

Perl scripting

Automation

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Siemens Tessent

Advantest

Teradyne

Job description

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED seeks a Design-for-Test (DFT) Engineer to drive DFT across complex hierarchical SoC/ASIC designs, insert scans, perform compression, and verify DFT effectiveness.

You will collaborate with Physical design and ATE teams to ensure first-pass silicon success and robust test strategy. The role involves hands-on DFT insertion and verification, including ATPG pattern generation and timing validation, with strong scripting in TCL, Python or Perl to