Senior / Analog Layout Engineer

AUREXIS TECH PTE. LTD.; Singapore; On-site; SGD 60,000 - 100,000; Full time

Job summary

AUREXIS TECH PTE. LTD. is seeking an experienced layout engineer to work on analog, digital and mixed-signal circuits in Singapore.

You will own the layout of major custom IP blocks and collaborate with analog designers on floorplanning and layout implementation. The role requires hands-on expertise in analog layout design, CMOS circuit theory, and layout verification using Cadence Virtuoso and Mentor Calibre, with experience in LVS, DRC, ERC, ESD, latch-up and reliability.

Qualifications

• Degree in Electrical/Electronics/Computer Engineering or equivalent.
• CMOS circuit theory knowledge.
• Solid experience in analog layout design.
• Layout design and verification using Cadence Virtuoso and Mentor Calibre.
• Experience in LVS, DRC, ERC, ANT, ESD, latch-up, EMIR and reliability.
• Good understanding of signal and clock shielding and isolation techniques.
• Good communication and teamwork skills.

Responsibilities

• Design layout for analog, digital and mixed-signal circuits.
• Own layout of major custom IP blocks.
• Collaborate with analog designers on floorplanning and layout implementation.
• Perform physical and electrical verification (DRC, LVS, EM/IR, ERC, PERC latch up, PERC ESD).
• Review resource deliverables and ensure quality and milestones.
• Plan schedules and drive blocks to meet project timelines.

Skills

CMOS circuit theory

Analog layout design

Layout verification

Communication skills

Team player

Scheduling

Education

Degree in Electrical/Electronics/Computer Engineering

Tools

Cadence Virtuoso

Mentor Calibre

Job description

Main Responsibilities

• Design layout for analog, digital and mixed-signal circuits.
• Own layout of major custom IP blocks.
• Work closely with analog designers on floorplanning and layout implementation.
• Physical and electrical verification includeDRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD
• Review resource deliverables and ensure quality/milestone completion.
• Plan schedules and drive assigned blocks to meet project timelines.

Main Requirements

• Degree in Electrical/ Electronics/ Computer Engineering or equivalent with minimum 3 years of relevant experiences.
• Must have knowledge of CMOS circuit theory
• Solid experience in analog layout design
• Layout design and verification experience using Cadence Virtuoso and Mentor Calibre
• Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
• Good understanding of signal and clock shielding and isolation techniques
• Good communication skill and team player