Senior Layout Engineer for Analog & SoC Integration

CURIOUS TEK PTE. LTD.; Singapore; Sur place; SGD 90 000 - 120 000; Plein temps

Résumé du poste

Curious Tek PTE. LTD. in Singapore is seeking an experienced layout engineer to design digital and analog IC layouts, and to support SoC integration with the front-end team. The role requires hands-on expertise in CMOS layouts and strong problem-solving skills to fix DRC/LVS issues.

The ideal candidate holds a bachelor’s degree in Electrical & Electronic Engineering and has 5+ years of layout experience, with proficiency in Cadence, Synopsys, and Mentor Calibre.

Qualifications

• Bachelor’s degree in Electrical & Electronic Engineering or related field with background on IC design (Analog & Digital)
• 5+ years of experience in layout design
• Knowledge of EDA tools (Cadence, Synopsys, Mentor Calibre)
• Knowledge of circuit reliability considerations (ESD, latch-up, aging, EMIR)
• Ability to troubleshoot and rectify layout verification errors on DRC/LVS; familiar with layout signoff flow
• Strong communication, independence, and teamwork

Responsabilités

• Develop digital and analog layout across technologies (e.g., CMOS)
• Layout analog and IO circuits
• Analyse and rectify layout verification issues
• Support front-end team for SoC integration

Connaissances

Layout design

EDA tools

Troubleshooting

Communication

Formation

Bachelor’s degree in Electrical & Electronic Engineering

Outils

Cadence

Synopsys

Mentor Calibre

Description du poste

Curious Tek PTE. LTD. in Singapore is seeking an experienced layout engineer to design digital and analog IC layouts, and to support SoC integration with the front-end team. The role requires hands-on expertise in CMOS layouts and strong problem-solving skills to fix DRC/LVS issues.

The ideal candidate holds a bachelor’s degree in Electrical & Electronic Engineering and has 5+ years of layout experience, with proficiency in Cadence, Synopsys, and Mentor Calibre.