RISC-V Front-End RTL Engineer with Custom Extensions

Bitdeer Technologies Group; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

Bitdeer Technologies Group is seeking an experienced hardware/SoC engineer to drive CPU core integration and customization for ASIC front‑end requirements. You will tailor a RISC‑V based IP, modify RTL, and collaborate across performance, synthesis, and P&R teams to ensure design constraints are met.

The role requires strong Verilog/SystemVerilog experience, a deep understanding of CPU architectures, and a proactive approach to automation and debugging across pre‑ and post‑silicon stages.

Qualifications

• Master’s degree (preferred) or Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture.
• Familiarity with the RISC‑V ISA, especially custom extensions and CSRs.
• Strong understanding of CPU architecture, IP feature tailoring and pruning.
• Extensive Verilog RTL development experience with industry-standard tools.

Responsibilities

• Integrate a commercial RISC-V core soft IP with external accelerators via custom extension interfaces.
• Tailor microarchitecture to meet performance, power, and area targets.
• Modify RTL (Verilog/SystemVerilog) to support customized architectural features.
• Collaborate with performance, middle-end and back-end engineers to optimize IP integration and meet design constraints.
• Drive ASIC Front-End execution, including synthesis support, STA closure, power reduction, and floorplanning.

Skills

CPU core integration

RISC‑V expertise

RTL design

Verilog/SystemVerilog

IP feature tailoring

Synthesis/DFT/STA

Power/area optimization

Cross-functional collaboration

Automation scripting

CP/U back-end collaboration

Education

Master’s or Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

Verilog SystemVerilog

Job description

Bitdeer Technologies Group is seeking an experienced hardware/SoC engineer to drive CPU core integration and customization for ASIC front‑end requirements. You will tailor a RISC‑V based IP, modify RTL, and collaborate across performance, synthesis, and P&R teams to ensure design constraints are met.

The role requires strong Verilog/SystemVerilog experience, a deep understanding of CPU architectures, and a proactive approach to automation and debugging across pre‑ and post‑silicon stages.