Senior Front-End CPU RTL Engineer

RICORE TECHNOLOGY PTE. LTD.; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

RICORE TECHNOLOGY PTE. LTD. is seeking a highly skilled engineer to lead micro-architecture design and RTL implementation for a high-performance CPU front-end pipeline.

You will work on instruction fetch, branch prediction, decode, dispatch, and instruction queue modules, ensuring robust, scalable architecture. Ideal candidates have 3+ years of RTL design experience in CPU/SoC front-end, with strong Verilog/SystemVerilog skills and familiarity with RISC-V/ARM.

Qualifications

• Bachelor's degree or above in Microelectronics, Computer Architecture, Electrical Engineering or related disciplines.
• 3+ years RTL design experience in CPU/SoC front-end; proficient in Verilog/SystemVerilog.
• Strong knowledge of instruction fetch, branch prediction, and decode pipelines; familiarity with RISC-V/ARM.

Responsibilities

• Design micro-architecture and RTL for CPU front-end: fetch, branch predict, decode, dispatch, and instruction queue.
• Design pipeline hazard detection, dependency resolution, conflict handling and out-of-order scheduling.
• Conduct PPA optimization to improve throughput, branch accuracy, and latency.
• Collaborate with verification teams for module- and system-level verification.
• Support SoC integration and pre-tapeout optimization.
• Deliver design docs and participate in architecture reviews.

Skills

RTL design

Verilog/SystemVerilog

CPU front-end architecture

PPA optimization

Debugging

Documentation

Cross-team collaboration

Education

Bachelor's degree or above in Microelectronics / Computer Architecture

Tools

EDA tools

Job description

RICORE TECHNOLOGY PTE. LTD. is seeking a highly skilled engineer to lead micro-architecture design and RTL implementation for a high-performance CPU front-end pipeline.

You will work on instruction fetch, branch prediction, decode, dispatch, and instruction queue modules, ensuring robust, scalable architecture. Ideal candidates have 3+ years of RTL design experience in CPU/SoC front-end, with strong Verilog/SystemVerilog skills and familiarity with RISC-V/ARM.