Senior Front-End ASIC/CPU Engineer (RISC-V)

Bitdeer Group; Singapore; On-site; SGD 70,000 - 90,000; Full time

Benefits offered by this job

Attractive welfare benefits

Training and mentoring opportunities

Job summary

Bitdeer Group in Singapore is seeking a skilled CPU Integration Engineer to drive the implementation of RISC-V core integration and feature tailoring for advanced computing solutions. Candidates should possess a Master’s or Bachelor’s degree in a relevant field and significant Verilog RTL experience.

Join a culture valuing diversity and innovation while making impactful contributions to the digital asset industry. Opportunities for personal growth, autonomy, and competitive welfare benefits are offered.

Qualifications

• Master’s degree (preferred) or Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Familiarity with the RISC-V ISA and custom extensions.
• Extensive Verilog RTL development experience.

Responsibilities

• Responsible for integrating a commercial RISC-V core soft IP with external accelerators.
• Perform feature tailoring of the CPU soft IP.
• Work closely with different engineering teams to ensure seamless IP integration.

Skills

RISC-V expertise

Verilog RTL development

CPU architecture understanding

Scripting languages (Python, Perl, Shell, TCL)

Education

Master’s degree or Bachelor’s in Electrical Engineering/Computer Science

Tools

Industry-standard design tools

Job description

Bitdeer Group in Singapore is seeking a skilled CPU Integration Engineer to drive the implementation of RISC-V core integration and feature tailoring for advanced computing solutions. Candidates should possess a Master’s or Bachelor’s degree in a relevant field and significant Verilog RTL experience.

Join a culture valuing diversity and innovation while making impactful contributions to the digital asset industry. Opportunities for personal growth, autonomy, and competitive welfare benefits are offered.