Senior/Staff Front-End Design Engineer (RTL Design - RiscV)

Bitdeer Technologies Group; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

Bitdeer Technologies Group is seeking an experienced hardware/SoC engineer to drive CPU core integration and customization for ASIC front‑end requirements. You will tailor a RISC‑V based IP, modify RTL, and collaborate across performance, synthesis, and P&R teams to ensure design constraints are met.

The role requires strong Verilog/SystemVerilog experience, a deep understanding of CPU architectures, and a proactive approach to automation and debugging across pre‑ and post‑silicon stages.

Qualifications

• Master’s degree (preferred) or Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture.
• Familiarity with the RISC‑V ISA, especially custom extensions and CSRs.
• Strong understanding of CPU architecture, IP feature tailoring and pruning.
• Extensive Verilog RTL development experience with industry-standard tools.

Responsibilities

• Integrate a commercial RISC-V core soft IP with external accelerators via custom extension interfaces.
• Tailor microarchitecture to meet performance, power, and area targets.
• Modify RTL (Verilog/SystemVerilog) to support customized architectural features.
• Collaborate with performance, middle-end and back-end engineers to optimize IP integration and meet design constraints.
• Drive ASIC Front-End execution, including synthesis support, STA closure, power reduction, and floorplanning.

Skills

CPU core integration

RISC‑V expertise

RTL design

Verilog/SystemVerilog

IP feature tailoring

Synthesis/DFT/STA

Power/area optimization

Cross-functional collaboration

Automation scripting

CP/U back-end collaboration

Education

Master’s or Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

Verilog SystemVerilog

Job description

About Bitdeer:

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud.
Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This includes equipment procurement, transport logistics, datacenter design and construction, equipment management, and network and facility operations. Bitdeer also offers advanced cloud capabilities to customers with a high demand for artificial intelligence.
Headquartered in Singapore, Bitdeer operates globally with a diversified 3 GW energy portfolio, and deploys Bitcoin mining and HPC datacenters in the United States, Bhutan, Norway, Canada, Malaysia, and Ethiopia.

What you will be responsible for:

• CPU Core Integration & Customization: Responsible for the integration of a commercial RISC-V core soft IP with external accelerators utilizing RISC-V custom extension instruction interfaces.
• Specification & Feature Tailoring: Perform feature tailoring of the CPU soft IP, configuring the microarchitecture to strip away unnecessary features and meet strict performance, power, and area (PPA) requirements.
• RTL Modification: Perform targeted Verilog/SystemVerilog RTL design modifications and enhancements, primarily focusing on the processor front‑end and the control path to support customized architectural features.
• Cross-Functional Collaboration: Work closely with performance engineers, middle‑end engineers, and back‑end (physical design) engineers to ensure seamless IP integration, optimize system‑level performance, and meet physical design constraints.
• ASIC Front-End Execution: Drive Front-End (FE) ASIC implementation steps, including supporting synthesis, static timing analysis (STA) closure, power reduction, and floorplanning efforts to optimize PPA.
• Verification & Debugging: Contribute to design verification (DV) efforts and assist in debugging complex logic issues across both pre‑silicon and post‑silicon stages.

How you will stand out:

• Education: Master’s degree (preferred) or Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, with a strict focus on computer architecture.
• RISC‑V Expertise: Familiarity with the RISC‑V ISA, particularly custom extensions, extension instruction interfaces, privilege modes, and Control and Status Registers (CSRs).
• Core Integration & Architecture: Strong understanding of CPU architecture and logic design, with prominent, hands‑on experience in CPU core integration, technical specification drafting, and IP feature tailoring/pruning.
• RTL Design: Extensive Verilog RTL development experience using industry‑standard tools.
• Collaboration Experience: Proven working experience collaborating with performance modeling/engineering teams, middle‑end engineers (synthesis/DFT), and back‑end (P&R) engineers.
• Preferred Knowledge: (1) Synthesis flows, linting, CDC/RDC analysis, and static timing analysis (STA). (2) SoC‑level power‑saving techniques, clocking architectures, reset/power‑up sequences, and low‑power microarchitecture development. (3) DFT, DFX, MBIST techniques.
• Automation: Comfort with writing in scripting languages (Python, Perl, Shell, TCL) to automate design.

What you will experience working with us:

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and exciting start‑up spirit;
• Fast‑growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.

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Bitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. Bitdeer does not discriminate against employees or applicants based on conditions such as race, colour, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.