Senior SoC Integration Engineer (RISC-V)

Bitdeer (NASDAQ: BTDR); Singapore; On-site; SGD 150,000 - 180,000; Full time

Job summary

Bitdeer is seeking an experienced SoC Design Engineer to advance next‑generation systems. The role focuses on integrating RISC processors into SoCs, configuring caches, MMU/MPU, and interconnects, while coordinating with verification and firmware teams to enable boot and OS bring‑up.

The candidate will work across RTL, architecture, verification, and software teams to optimize performance, power, and system integration while collaborating with third‑party IP vendors.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• 5+ years of SoC design, processor integration, or related semiconductor experience.
• Strong experience integrating RISC processors, especially RISC-V, into complex SoC platforms.
• Solid understanding of processor architecture including pipelines, caches, MMU/MPU/PMP.
• Experience with AMBA protocols (AXI4/AHB/APB).

Responsibilities

• Configure and integrate RISC processor IP into SoC platforms.
• Customize processor features: cache, MMU/MPU, PMP, debug, IRQs, privilege modes.
• Integrate processor subsystems with AXI/AHB/APB interconnects and PLIC/GIC/NVIC.
• Develop RTL integration logic, wrappers, and system glue.
• Collaborate with verification to develop test plans and debug simulation issues.
• Work with firmware to enable bootloader, BSP, and OS bring-up.
• Analyze and resolve system-level performance, power, and integration issues.
• Review third-party IP documentation and coordinate IP integration.

Skills

RISC-V integration

Arm integration

RTL design

AMBA protocols

System bring-up

Cross-functional collaboration

Verilog/SystemVerilog

Debug architecture

Bootloader/firmware interaction

Performance/power optimization

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

VCS

Xcelium

Questa

Verdi

Job description

Bitdeer is seeking an experienced SoC Design Engineer to advance next‑generation systems. The role focuses on integrating RISC processors into SoCs, configuring caches, MMU/MPU, and interconnects, while coordinating with verification and firmware teams to enable boot and OS bring‑up.

The candidate will work across RTL, architecture, verification, and software teams to optimize performance, power, and system integration while collaborating with third‑party IP vendors.