Senior SoC Design Engineer (RISC-V/Arm)

Bitdeer Technologies Group; Singapore; On-site; SGD 120,000 - 180,000; Full time

Benefits offered by this job

Attractive welfare benefits

Training and mentoring

Job summary

Bitdeer in Singapore seeks an experienced SoC Design Engineer to develop next-generation System-on-Chip solutions. You will implement RISC processors (RISC-V or Arm), configure caches, MMU/MPU, and bring-up subsystems within complex SoC platforms.

You will collaborate with architecture, RTL, verification, firmware and software teams through the full development lifecycle, optimize performance, and review third‑party IP while driving integration with cross-functional teams.

Qualifications

• 5+ years in SoC design or processor integration
• Strong RTL skills with Verilog/SystemVerilog
• Experience with RISC-V cores and ARM is a plus
• Familiarity with AMBA protocols and boot flow

Responsibilities

• Configure and integrate RISC processor IP into SoC platforms
• Customize processor features: cache, MMU/MPU, PMP, debug, interrupt controller
• Integrate processor subsystems with AXI/AHB/APB interconnects and PLIC/GIC/NVIC
• Develop RTL integration logic, wrappers and system glue logic
• Collaborate with verification teams to develop test plans and debug issues
• Work with firmware/software teams to enable bootloader, BSP and OS bring-up
• Analyze and resolve system-level performance and power issues
• Review third-party IP documentation and coordinate IP integration

Skills

RISC-V Integration

Verilog/SystemVerilog

AMBA AXI/ARB

RTL/SoC

Debug & Verification

Cross-functional Collaboration

Third-party IP Coordination

Education

Bachelor's or Master’s in Electrical/Computer Engineering

Tools

VCS

Xcelium

Questa

Verdi

Job description

Bitdeer in Singapore seeks an experienced SoC Design Engineer to develop next-generation System-on-Chip solutions. You will implement RISC processors (RISC-V or Arm), configure caches, MMU/MPU, and bring-up subsystems within complex SoC platforms.

You will collaborate with architecture, RTL, verification, firmware and software teams through the full development lifecycle, optimize performance, and review third‑party IP while driving integration with cross-functional teams.