Principal Front End Engineer

BITDEER DEVELOPMENT PTE. LTD.; Singapore; On-site; SGD 60,000 - 100,000; Full time

Job summary

A leading technology company in Singapore is seeking an experienced engineer to implement Verilog RTL for NPU/CPU design. The role involves collaboration with hardware and software teams, focusing on architecture definition and performance optimization. Candidates should have a Master's or Bachelor's degree in relevant fields and expertise in Verilog development. The company offers an inclusive work culture, opportunities for growth, and attractive benefits.

Benefits

Attractive welfare benefits

Personal development opportunities

Networking with industry pioneers

Qualifications

• Experience with Verilog RTL development in an NPU/CPU/SoC/ASIC environment.
• Strong understanding of logic design and architecture.
• Familiarity with synthesis, place & route, and timing closure.

Responsibilities

• Implement Verilog RTL for sections of the NPU/CPU/NoC core pipeline.
• Support synthesis and performance optimization.
• Contribute to design verification and debugging.

Skills

Verilog RTL development

NPU/CPU architecture understanding

Problem-solving skills

Scripting languages (Perl, Shell, TCL)

Power-saving techniques

Education

Master's or Bachelor's in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Industry-standard Verilog tools

Job description

About Bitdeer

Bitdeer Technologies Group (Nasdaq: BTDR) is a world-leading technology company for Bitcoin mining. Bitdeer is committed to providing comprehensive computing solutions for its customers. The Company handles complex processes involved in computing such as equipment procurement, transport logistics, datacenter design and construction, equipment management, and daily operations. The Company also offers advanced cloud capabilities to customers with high demand for artificial intelligence. Headquartered in Singapore, Bitdeer has deployed datacenters in the United States, Norway, and Bhutan.

What you will be responsible for

• Implement Verilog RTL for various sections of the NPU/CPU/NoC core pipeline and related logic.
• Work with hardware and software engineers to define high-level architecture and microarchitecture of next-generation high-performance cores.
• Support synthesis, timing closure, power reduction, and floorplanning efforts to optimize performance and efficiency.
• Contribute to design verification and assist in debugging issues across pre-silicon and post-silicon stages.

How you will stand out

• Master’s degree (preferred) or Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture
• Verilog RTL development experience with industry-standard tools in a NPU/CPU, SoC, or ASIC environment.
• Strong understanding of NPU/CPU architecture and logic design.
• Familiarity with power-saving techniques and microarchitecture development.
• Awareness of synthesis, place & route (P&R), and timing closure concepts.
• Strong problem-solving and debugging skills.
• Background in ASIC implementation, particularly synthesis flow and static timing analysis.
• Knowledge of Design-for-Test (DFT) and Design-for-Debug (DFD) techniques.
• Experience with clocking, reset sequences, power-up sequences, and power management.
• Exposure to physical design and verification methods.
• Familiarity with x86 or ARM ISA.
• Comfort with scripting languages (Perl, Shell, TCL) to automate design tasks.

What you will experience working with us

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and exciting start-up spirit;
• Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.

Bitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. Bitdeer does not discriminate against employees or applicants based on conditions such as race, colour, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.