Principal Engineer / Senior Engineer (Thin Film CVD - Process)

Vanguard International Semiconductor Corporation; Singapore; On-site; SGD 70,000 - 120,000; Full time

Job summary

Vanguard International Semiconductor Corporation in Singapore seeks an experienced engineer to analyze SPC charts, perform DOE data analysis and drive yield improvements. You will coordinate with Equipment and Mfg.

teams to optimize process windows and ensure recipe/content compliance, while mentoring junior staff and maintaining TS16949 quality standards. The role requires strong leadership, deep analytical capability, and proficiency in JMP, Klarity ACE, PROMIS and RMS, with the ability to

Qualifications

• Min 5 years of wafer fabrication process experience.
• Experience with Thin Film CVD processes.
• Excellent teamwork and interpersonal, with strong written skills.
• Strong leadership to guide junior engineers.
• Strong analytical and logical thinking abilities.
• High integrity with leadership attributes.
• Proactive, accountable and able to work under pressure.
• Proficient in MS Office applications.

Responsibilities

• Analyse SPC charts, know PR rules and annotate to maintain quality troubleshooting rate for SPC OOC.
• Monitor critical SPC charts daily; perform process window study and suggest improvements to reduce OOC and boost CPK.
• Analyse split lot, DOE data, ET; sort yield using JMP and Klarity ACE.
• Create SPC charts, DCOP and modify SLDB using PROMIS (Si-View).
• Upload/check recipes to ensure recipe content compliance using RMS.
• Follow up on SPSR, MRB, 8D, TECN, or ECN spec updates.
• Setup and troubleshoot recipes/job files in all metrology tools within the Module.
• Provide pass-down support to troubleshoot process issues; establish CAS/procedures with cross-dept teams.
• Startup and qualify new processes and equipment; work with Equipment Engineer on acceptance; understand R&R concepts.
• Work to reduce process constraints for greater manufacturing flexibility.
• Perform process matching between equipment to reduce variation; use DOE to identify factors for better tool matching.
• Participate in CIP programs to optimize process window, cost, yield and productivity.
• Represent module in cross-functional teams to address yield excursions and engage in cross-fab benchmarking.
• Self-audit and update specifications/documentation to meet TS16949 Quality Standard requirements.
• Adhere to housekeeping and safety rules in office and FAB.
• Provide feedback/training to AEs or Techs on troubleshooting, process understanding, decision making and risk assessment.

Tools

JMP

Klarity ACE

PROMIS (Si-View)

RMS

MS Office

Job description

• Analyse SPC chart. Know all the PR rules and their significance. Do proper annotation to maintain quality troubleshooting rate for SPC OOC. Understand Cp and Cpk indices
• Monitor critical SPC charts daily. Perform process window study and provide improvement plan to reduce OOC and improve CPK
• Analyse split lot, DOE data, ET, sort yield using JMP, Klarity ACE.
• Create SPC charts, DCOP and modify SLDB using PROMIS (Si-View).
• Upload recipe, check recipe and ensure recipe content compliance using RMS.
• Follow up on SPSR, MRB, 8D, TECN, or spec update with ECN.
• Setup and troubleshoot in recipes/ job files in all metrology tools within the Module.
• Follow up on pass down to troubleshoot process issues. Establish CAS / procedures to be followed and work with other departments for resolution if required.
• Startup and qualify new process and new equipment within scheduled timeline. Work closely with the Equipment Engineer on new equipment acceptance. Know the concept of repeatability and reproducibility (R&R) run.
• Work on reducing process constraint so that Mfg. can have more flexibility.
• Perform process matching between equipment’s to reduce variation and analysis / DOE to find factors for better tool matching.
• Participate in CIP programs to optimize process window, cost, yield, and productivity.
• Work as a team with both Equipment and Mfg. Engineers to meet Module objectives. Work to meet the key indices of Uptime and OEE goals.
• Represent own Module to attend cross-functional task team to address yield improvement/ excursion issues. Follow up with cross-fab benchmarking activities to engage the best-in-campus practices across fabs.
• Self-audit and update specifications/ documentation to meet TS16949 Quality Standard requirements.
• Follow good housekeeping and safety rules in office and FAB.
• Provide feedback/ training to AEs or Techs on their troubleshooting skills, understanding of processes, decision making, risk assessment.

Requirements:

• Degree in Electrical / Electronics / Mechanical /Microelectronics / Chemical Process / Chemistry / Physics/ Material Science/Material Engineering
• Min5 years of relevant work experience in Wafer fabrication process and Thin Film CVD Process.
• An excellent team player with good interpersonal, communication and written skills
• Strong leadership capability to lead and guide junior engineers
• Strong logical thinking capability and good analytical skill
• High level of integrity with strong leadership attributes to lead and coach a team
• Proactive and highly committed with good ownership and accountability
• Able to adapt in a fast-paced environment and work under pressure
• Proficient in MS Office Applications

We regret that only shortlisted candidates will be notified.