Packaging Process Engineer — 2.5D/3D Tech & Cross‑Team Impact

PICOHEART (SG) PTE. LTD.; Singapore; On-site; SGD 90,000 - 120,000; Full time

Job summary

The Silicon Platform Team acts as the core R&D middleware group for chip development within ByteDance. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM).

The team also oversees tape-out, mass production, packaging, testing, and board-level verification.

Qualifications

• Master's degree or above in relevant microelectronics field with at least 2 years of experience.
• Experience in 2D/2.5D/3D packaging process integration with at least one technology (FCBGA, FCCSP, MCM, 2.5D, 3D).
• Familiar with packaging process flow and DRM.
• Proficient in process problem-solving methodologies, with experience in root cause analysis and corrective action implementation for packaging process failures.
• Strong cross-team communication skills.

Responsibilities

• Process Integration Management: interface between internal teams and OSATs, fabs, and substrate vendors to resolve packaging issues.
• Project Execution & Risk Control: follow up with suppliers to meet process requirements and ensure smooth production flow.
• R&D Pre-research: lead process research, drive vendors to meet technical requirements, and conduct pre-verification of new packaging technologies.
• Cross-team Collaboration: coordinate with packaging design, thermal/stress simulation, and product teams to align process constraints and resolve cross-domain technical issues.

Skills

Cross-team communication

Root cause analysis

Packaging process knowledge

Education

Master's degree or above in Microelectronics/Electronics/Materials Science/Mechanical Engineering or related fields

Tools

DRM (Design Rules)

Job description

The Silicon Platform Team acts as the core R&D middleware group for chip development within ByteDance. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM).

The team also oversees tape-out, mass production, packaging, testing, and board-level verification.