Chip Synthesis & STA Engineer (Singapore)

ByteDance; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

The ByteDance Silicon Platform Team is the core R&D middleware group for chip development, covering the full design flow from architecture to tape-out and mass production. You will design and optimize RTL/architectures, perform timing signoff, and implement low-power techniques in a collaborative environment across frontend and backend teams.

We value strong Verilog/SystemVerilog skills, RTL-to-GDSII expertise, and proficiency with leading EDA tools for efficient power-optimized solutions in

Qualifications

• Bachelor’s or Master’s degree in electrical/electronic or related field.
• 3+ years of IC design experience focusing on SDC, synthesis, timing signoff, low-power implementation, and power optimization.
• Proficiency in Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Fusion Compiler, Genus, Innovus, PrimeTime/Tempus, Formality, Conformal LP).

Responsibilities

• Perform logic synthesis and design optimization for architectures and RTLs.
• Timing constraints preparation and tuning, and conduct hierarchical/full-chip STA signoff and timing closure.
• Implement low-power design techniques and constraints (UPF, clock gating, power gating, dynamic voltage scaling).
• Formal verification & equivalence checking using formal verification tools (Conformal, Formality).
• Work with front-end engineers for architectural exploration and planning.
• Work with backend engineers on floorplanning, place & route (P&R), congestion analysis, and timing bottlenecks.

Skills

Verilog/SystemVerilog

Synthesis

Low-power design

Power optimization

Timing analysis

Education

Bachelor’s or Master’s in electrical engineering, computer engineering, or related field

Tools

Fusion Compiler

Genus/Innovus+

PrimeTime/Tempus

Formality

Conformal LP

Job description

The ByteDance Silicon Platform Team is the core R&D middleware group for chip development, covering the full design flow from architecture to tape-out and mass production. You will design and optimize RTL/architectures, perform timing signoff, and implement low-power techniques in a collaborative environment across frontend and backend teams.

We value strong Verilog/SystemVerilog skills, RTL-to-GDSII expertise, and proficiency with leading EDA tools for efficient power-optimized solutions in