SoC DFT Engineer – Test Vector Bring-Up

ByteDance; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

ByteDance's Silicon Platform Team leads the R&D middleware efforts for chip development, covering DFT, synthesis, STA, power integrity, and tape-out processes. The team collaborates with front-end chip teams to push R&D progress and mass production deployment for chips.

The role focuses on DFT-related work in SoC chips, coordinating with STA, physical design, and test engineers to ensure proper timing, power, and test coverage across silicon bring-up and validation stages.

Qualifications

• Master's degree or above in Microelectronics, Electronics, Computer Science or related fields.
• More than 2 years of DFT work experience.
• Proficient in scripting (TCL, Perl, Python, etc.).

Responsibilities

• Responsible for DFT-related work in SoC chips, including Scan, MBIST, ATPG, Boundary Scan, IP test etc.
• Collaborate with STA, physical design, and power engineers to debug and resolve DFT-related Timing/Power-IR problems.
• Work with test engineers to bring up test vectors on silicon and ensure successful testing.

Skills

Scripting

DFT knowledge

Problem solving

Education

Master's or higher in Microelectronics/ Electronics/ CS

Tools

DFT EDA Tools

Job description

ByteDance's Silicon Platform Team leads the R&D middleware efforts for chip development, covering DFT, synthesis, STA, power integrity, and tape-out processes. The team collaborates with front-end chip teams to push R&D progress and mass production deployment for chips.

The role focuses on DFT-related work in SoC chips, coordinating with STA, physical design, and test engineers to ensure proper timing, power, and test coverage across silicon bring-up and validation stages.