Package-Silicon Integration Engineer (Early Career)

Micron Technology, Inc; Singapore; On-site; SGD 60,000 - 80,000; Full time

Job summary

Micron Technology, Inc. is looking for an Engineer in Package-Silicon Integration in Singapore. This role supports NAND package and silicon integration for next-generation memory products, providing early-career engineers with structured exposure to semiconductor packaging and integration risks.

Responsibilities include assisting with chip-package interaction assessments and collaborating with cross-functional teams. Candidates should have a Bachelor's or Master's degree in Engineering, with less than 2 years of experience.

The position offers mentoring, guidance, and an opportunity to build foundational technical skills while contributing to team objectives.

Qualifications

• Less than 2 years of relevant experience, including internships or co-op programs in semiconductor, materials, or manufacturing.
• Strong attention to detail and willingness to learn new tools, processes, and technologies.
• Good written and verbal communication skills, with the ability to collaborate effectively in a team environment.

Responsibilities

• Support chip-package interaction assessments and document results.
• Assist in investigating wafer dicing and integration topics.
• Participate in DFMEA / PFMEA activities and track action items.
• Work with teams to support yield, quality, and manufacturability investigations.
• Prepare technical documentation for design reviews and project updates.

Skills

Semiconductor manufacturing and/or packaging concepts

Data analysis

Microsoft Excel

Problem-solving methods (FMEA, DOE)

Education

Bachelor’s or Master’s degree in Engineering (Mechanical, Materials Science, Electrical, Chemical)

Tools

Microsoft Word

Microsoft PowerPoint

Job description

Micron Technology, Inc. is looking for an Engineer in Package-Silicon Integration in Singapore. This role supports NAND package and silicon integration for next-generation memory products, providing early-career engineers with structured exposure to semiconductor packaging and integration risks.

Responsibilities include assisting with chip-package interaction assessments and collaborating with cross-functional teams. Candidates should have a Bachelor's or Master's degree in Engineering, with less than 2 years of experience.

The position offers mentoring, guidance, and an opportunity to build foundational technical skills while contributing to team objectives.