NAND CMP Principal Engineer — Innovate & Lead

Micron Technology, Inc.; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

Micron Technology, Inc. in Singapore seeks a Principal Engineer to lead CMP process development for next-gen NAND devices. You will drive the 3D NAND CMP program, optimize procedures, and push for manufacturability of future nodes while collaborating with global teams and vendors.

The role requires hands-on CMP equipment operation and deep understanding of integration constraints across deposition, etch, and metrology, with a focus on advancing yield and device performance.

Qualifications

• Hands-on CMP equipment operation (AMAT LKP, EBARA-300X).
• Experience in dielectrics/metals CMP on 3D NAND or memory tech.
• Understanding of integration constraints related to film deposition and upstream/downstream processes.

Responsibilities

• Develop and optimize CMP procedures to improve product quality and reliability.
• Improve process margins to meet yield goals for 3D NAND.
• Lead experiments to widen process margins and evaluate manufacturability of next-node solutions.
• Collaborate with vendors to meet integration requirements for 3D NAND nodes.
• Design and implement advanced process monitoring and control methodologies.
• Provide strategic roadmap for N+, N++ and future NAND nodes.
• Mentor new hires and engage with global teams.

Skills

CMP process development

CMP equipment operation

3D NAND memory

Planarization fundamentals

AI for process optimization

Education

Masters/PhD in relevant field

Bachelor's degree in related field

Tools

AMAT LKP

EBARA-300X

Optical metrology

Profilometry

Job description

Micron Technology, Inc. in Singapore seeks a Principal Engineer to lead CMP process development for next-gen NAND devices. You will drive the 3D NAND CMP program, optimize procedures, and push for manufacturability of future nodes while collaborating with global teams and vendors.

The role requires hands-on CMP equipment operation and deep understanding of integration constraints across deposition, etch, and metrology, with a focus on advancing yield and device performance.