FOWLP & Advanced Packaging Research Engineer

A*STAR RESEARCH ENTITIES; Singapore; On-site; SGD 150,000 - 210,000; Full time

Job summary

A*STAR RESEARCH ENTITIES is seeking a senior research engineer to lead process integration for high-density multi-chip fan-out wafer level packaging (FOWLP) projects. You will develop new capabilities, design experiments, and optimize lithography, plating and etching steps to meet industry partner requirements.

You will mentor junior colleagues, coordinate with multidisciplinary teams, publish findings in journals and conferences, and contribute to workforce development in semiconductor

Qualifications

• Bachelor's or Master's degree in engineering or sciences.
• 5–10 years in semiconductor device fabrication process integration.
• Hands-on lithography, plating, etching, RDL and bumping experience.
• Knowledge of wafer-level fabrication and advanced packaging tech.
• Strong analytical, data interpretation and design of experiments skills.
• Excellent written and verbal communication.
• Ability to collaborate across OEMs, customers and internal teams.

Responsibilities

• Process integration development for high-density multi-chip FOWLP.
• Develop capabilities for fine pitch RDL, micro bumping, multi-layer RDL.
• Establish novel RDL-first and mold-first FOWLP integration flows.
• Plan short loops with module teams for materials evaluation.
• Collaborate with industry partners to resolve issues and drive quality.
• Lead experiments for process characterization to improve yield.
• Mentor junior colleagues and support capability development
• Publish findings at journals and conferences; contribute to workforce growth

Skills

Analytical skills

Problem-solving

Data analysis

Design of experiments

Communication

Collaboration

Multitasking

Education

Bachelor's/Master's in engineering

Tools

Lithography

Plating

Etching

RDL

Bumping

Wafer-level packaging

Job description

A*STAR RESEARCH ENTITIES is seeking a senior research engineer to lead process integration for high-density multi-chip fan-out wafer level packaging (FOWLP) projects. You will develop new capabilities, design experiments, and optimize lithography, plating and etching steps to meet industry partner requirements.

You will mentor junior colleagues, coordinate with multidisciplinary teams, publish findings in journals and conferences, and contribute to workforce development in semiconductor