Lead FOWLP Process Integrator for AI Hardware

A*STAR - Agency for Science, Technology and Research; Singapore; Sur place; SGD 120 000 - 180 000; Plein temps

Résumé du poste

Institute of Microelectronics (IME) invites applications for a Lead Research Engineer – Process Integrator, Fan-Out Wafer Level Packaging. You will drive high-density, heterogeneous integration initiatives and collaborate with cross-functional teams to push FOWLP technology forward in AI applications.

Ideal candidates have 5–10 years in semiconductor fabrication, hands-on experience with lithography, etching and RDL/bumping, and a track record of mentoring.

Qualifications

• B.S. or M.S. in an engineering or science field with emphasis on manufacturing processes.
• Hands-on experience in lithography, plating, etching and RDL/bumping is advantageous.
• Strong understanding of wafer-level packaging and heterogeneous integration preferred.

Responsabilités

• Develop high-density multi-chip FOWLP process integration for AI/HPC and other applications.
• Advance capabilities: fine pitch RDL, micro bumping, multi-layer RDL, polymer damascene.
• Create RDL-first and mold-first integration flows to meet partner requirements.
• Plan short loops with module teams to evaluate processes and materials.
• Collaborate with industry partners to execute projects and resolve issues.
• Conduct experiments for process characterization to boost quality and yield.
• Support builds using developed packaging processes and integration.
• Lead capability development projects and mentor junior colleagues.
• Inspire and mentor talent in semiconductor tech and workforce development.
• Publish findings in journals and conferences.

Connaissances

Analytical thinking

Problem solving

Communication

Team collaboration

Data analysis

Formation

Engineering degree (Materials/Mechanical/Chemical/Electronics/Electrical)

Description du poste

Institute of Microelectronics (IME) invites applications for a Lead Research Engineer – Process Integrator, Fan-Out Wafer Level Packaging. You will drive high-density, heterogeneous integration initiatives and collaborate with cross-functional teams to push FOWLP technology forward in AI applications.

Ideal candidates have 5–10 years in semiconductor fabrication, hands-on experience with lithography, etching and RDL/bumping, and a track record of mentoring.