Lead ASIC Synthesis & Timing Optimization Engineer

Black Sesame Technologies (Singapore) Pte Ltd; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Black Sesame Technologies (Singapore) Pte Ltd seeks a Senior ASIC Implementation Engineer (Synthesis & STA) to join the Core IP Design Team. You will lead synthesis, low-power implementation, timing closure and work with physical design and SoC teams to deliver high-performance AI cores and ADAS chips.

The role emphasizes optimizing RTL for frequency, power and area, developing and maintaining synthesis and STA flows, and collaborating across design disciplines to ensure design convergence and

Qualifications

• Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• At least 3 years of relevant industry experience.
• Solid understanding of digital design and VLSI concepts.
• Proficiency in Verilog and SystemVerilog.
• Hands-on experience with synthesis tools, particularly Synopsys Design Compiler.
• Hands-on experience with static timing analysis using Synopsys PrimeTime.
• Experience with UPF-based low-power design and implementation flows.
• Experience with formal equivalence verification tools such as Cadence Conformal LEC and/or Synopsys Formality.
• Proficiency in scripting languages such as Tcl, Perl, and Python.
• Strong analytical, problem-solving, and communication skills.
• Excellent attention to detail and a strong willingness to learn.

Responsibilities

• Lead synthesis and optimization efforts for IP cores, with a focus on performance, power, and area (PPA).
• Collaborate with the physical design team on floorplanning, placement, routing, and timing closure.
• Work closely with the SoC team on clock, reset, timing, and power-related design requirements.
• Develop, maintain, and enhance synthesis, formal verification, and static timing analysis flows.
• Support the implementation and delivery of multiple complex IP blocks.
• Partner with SoC implementation engineers to integrate IP-level solutions into SoC-level design flows.
• Analyze implementation results and provide recommendations to improve RTL for higher frequency, lower power, and better physical design convergence.
• Identify opportunities to improve design methodologies, automation, and overall engineering efficiency.

Skills

Digital design

VLSI concepts

Verilog

SystemVerilog

Scripting languages

Education

Bachelor’s/Master’s/Ph.D. in Electrical Engineering or Computer Engineering

Tools

Synopsys Design Compiler

Synopsys PrimeTime

Cadence Conformal LEC

Synopsys Formality

Job description

Black Sesame Technologies (Singapore) Pte Ltd seeks a Senior ASIC Implementation Engineer (Synthesis & STA) to join the Core IP Design Team. You will lead synthesis, low-power implementation, timing closure and work with physical design and SoC teams to deliver high-performance AI cores and ADAS chips.

The role emphasizes optimizing RTL for frequency, power and area, developing and maintaining synthesis and STA flows, and collaborating across design disciplines to ensure design convergence and