ASIC STA Engineer

Black Sesame Technologies (Singapore) Pte Ltd; Singapore; Sur place; SGD 50 000 - 70 000; Plein temps

Résumé du poste

Black Sesame Technologies (Singapore) Pte Ltd invites motivated fresh graduates to join as ASIC STA Engineers. This entry-level position offers a pathway into ASIC timing analysis, with responsibilities spanning timing closure, verification, constraints, and collaboration across front-end and back-end teams to achieve chip PPA targets.

Ideal candidates hold a Master’s degree in electronics or related fields, possess foundational knowledge of timing analysis and synthesis, and are proficient in

Qualifications

• Master’s degree or higher in Electronics Engineering, Computer Science, or related field.
• Fundamental knowledge of ASIC timing analysis and synthesis.
• Familiarity with ASIC development process and design flow.
• Proficiency in programming languages such as Perl, Tcl, Python, or similar.
• Strong communication, collaboration, and proactive problem-solving abilities.

Responsabilités

• Timing Closure: Oversee timing closure at block level across the project.
• Timing Verification: Develop workflows for timing verification and closure.
• Timing Constraints: Generate and implement timing constraints (SDC) for performance.
• Timing Analysis: Perform detailed timing analysis to meet specs and metrics.
• Flows: Refine workflows to improve efficiency in timing analysis processes.
• Coordinator Role: Collaborate with front-end and back-end teams to meet PPA targets.

Connaissances

ASIC timing analysis

Synthesis

Perl

Tcl

Python

Timing closure

Timing constraints (SDC)

Formation

Master’s degree in Electronics Engineering

Master’s degree in Computer Science or related field

Outils

Verilog

Description du poste

Black Sesame Technologies is seeking motivated and talented fresh graduates to join our team as ASIC STA Engineers. This entry-level position offers an excellent opportunity for recent graduates to embark on a career in ASIC design and timing analysis. We are looking for individuals who are eager to learn and contribute to our innovative projects.

Responsibilities:

• Timing Closure: Oversee timing closure at the block level throughout the project lifecycle to ensure design integrity.
• Timing Verification: Develop and maintain methodologies and workflows for timing verification and closure, ensuring effective timing management.
• Timing Constraints: Collaborate with designers to generate and implement timing constraints (SDC) critical for design performance.
• Timing Analysis: Conduct detailed timing analysis to verify that designs meet required specifications and performance metrics.
• Flows: Assist in constructing and refining workflows to improve efficiency and effectiveness in timing analysis processes.
• Coordinator Role: Collaborate with front-end and back-end teams to achieve the chip PPA (Power, Performance, Area) target.

Qualification/ Requirements:

• Education: Master’s degree or higher in Electronics Engineering, Computer Science, or a related field.
• Fundamental knowledge of ASIC timing analysis and synthesis.
• Familiarity with the ASIC development process and design flow.
• Proficiency in programming languages such as Perl, Tcl, Python, or similar.
• Strong communication skills, a collaborative team approach, and a proactive attitude towards learning and problem-solving.