Layout Engineer (Semicon, One North)

PERSOL SINGAPORE PTE. LTD.; Singapore; On-site; SGD 61,000 - 73,000; Full time

Job summary

PERSOL SINGAPORE PTE. LTD. is seeking a Custom Layout Engineer to support the physical implementation of Foundation IP, Analog IP, and RFIC designs across advanced semiconductor process technologies.

You will lead full-chip layout development, physical verification, and optimization for power, performance, and area. Based at One North, this 12-month contract offers the chance to work with cross-functional teams on multi-node layouts, perform DRC/LVS checks, and ensure timely delivery of

Qualifications

• Bachelor's degree in Electrical/Electronic Engineering or related discipline.
• 3+ years of experience in custom layout, analog layout, RFIC, or Foundation IP.
• Hands-on experience with CMOS technologies (FinFET and/or GAA).

Responsibilities

• Perform custom layout implementation for IO/ESD, Analog, and RF circuits.
• Handle floorplanning, layout construction, physical verification, and sign-off activities.
• Conduct DRC, LVS, ERC, and other verification checks to ensure design quality.
• Collaborate with design, verification, and cross-functional teams to optimize layouts.
• Support project execution and provide regular status updates to stakeholders.
• Ensure timely delivery of high-quality layouts across multiple technology nodes.

Skills

Teamwork

Communication

Problem solving

Education

Bachelor's Degree in Electrical/Electronic Engineering

Tools

Cadence

Synopsys

Job description

We are seeking a Custom Layout Engineer to support the physical implementation of Foundation IP, Analog IP, and RFIC designs across advanced semiconductor process technologies. The role involves full-chip layout development, physical verification, and optimization for power, performance, and area (PPA).

Salary up to $6000

Contract: 12 months

Location: One North

Key Responsibilities

• Perform custom layout implementation for IO/ESD, Analog, and RF circuits.
• Handle floorplanning, layout construction, physical verification, and sign-off activities.
• Conduct DRC, LVS, ERC, and other verification checks to ensure design quality.
• Collaborate with design, verification, and cross-functional teams to optimize layouts.
• Support project execution and provide regular status updates to stakeholders.
• Ensure timely delivery of high-quality layouts across multiple technology nodes.

Requirements

• Bachelor's Degree in Electrical/Electronic Engineering or related discipline.
• 3+ years of experience in custom layout, analog layout, RFIC, or Foundation IP design.
• Hands-on experience with advanced CMOS technologies (FinFET and/or GAA).
• Proficiency in Cadence and/or Synopsys layout and verification tools.
• Strong understanding of DRC, LVS, ERC, ESD, SI/PI, EM/IR, and DFM concepts.
• Good communication and teamwork skills.

Preferred

• Experience with IO/ESD layout development.
• Familiarity with advanced foundry design rules and backend implementation flows.