Junior/Senior Memory Design Engineer (SRAM) (Semiconductor)

talent trader group pte. ltd.; Singapore; On-site; SGD 90,000 - 180,000; Full time

Job summary

talent trader group pte. ltd. is seeking a memory design engineer to define memory architecture and carry out end-to-end circuit design for embedded SRAM IP across multiple process technologies.

You will work closely with layout engineers, providing technical guidance for physical implementation of SRAM memory arrays and peripheral analog circuitry, and contribute to SRAM Compiler solutions. Ideal candidates hold a degree in microelectronics and have at least 3 years in analog/mixed-signal and

Qualifications

• Bachelor's or Master's degree in Microelectronics or a related field.
• Minimum 3 years of hands-on transistor-level analog and mixed-signal circuit design experience.
• Experience in memory design, including SRAM, ROM, and Register File architectures.
• Proficiency with industry-standard analog EDA tools (Cadence Virtuoso, Spectre, HSPICE, XA, FINESIM).
• Experience with SRAM chip testing and failure analysis is advantageous.
• Familiarity with CMOS, FinFET, and FD-SOI technologies across multiple process nodes.

Responsibilities

• Define memory architecture and carry out end-to-end circuit design for embedded SRAM IP across multiple process technologies, supporting memory types such as SP SRAM, DP SRAM, Register Files, and ROM.
• Work closely with layout engineers and provide technical guidance for the physical implementation of SRAM memory arrays and peripheral analog circuitry.
• Contribute to the development, enhancement, and maintenance of SRAM Compiler solutions.
• Support the creation of SRAM IP Design Kits (DK), including Verilog models, Liberty files, datasheets, bitmaps, and related collateral.
• Assist in the design, development, and validation of SRAM-related test chips.

Skills

Memory design

Analog/mixed-signal design

SRAM/ROM/Register file architectures

Transistor-level design

EDA tools

Test & failure analysis

CMOS/FinFET/FD-SOI technologies

Education

Bachelor’s or Master’s degree in Microelectronics

Tools

Cadence Virtuoso

Cadence Spectre

HSPICE

XA

FINESIM

Job description

Responsibilities

• Define memory architecture and carry out end-to-end circuit design for embedded SRAM IP across multiple process technologies, supporting memory types such as Single-Port (SP) SRAM, Dual-Port (DP) SRAM, Register Files, and ROM.
• Work closely with layout engineers and provide technical guidance for the physical implementation of SRAM memory arrays and peripheral analog circuitry.
• Contribute to the development, enhancement, and maintenance of SRAM Compiler solutions.
• Support the creation of SRAM IP Design Kits (DK), including deliverables such as Verilog models, Liberty files, datasheets, bitmaps, and related collateral.
• Assist in the design, development, and validation of SRAM-related test chips.

Requirements

• Bachelor's or Master's degree in Microelectronics or a related field
• Minimum of 3 years of hands-on experience in transistor-level analog and mixed-signal circuit design.
• Experience in memory design, including SRAM, ROM, and Register File architectures.
• Proficient in industry-standard analog EDA tools such as Cadence Virtuoso, Spectre, HSPICE, XA, FINESIM, and similar platforms for custom circuit design and simulation.
• Experience with SRAM chip testing and failure analysis is considered an advantage.
• Familiarity with advanced semiconductor technologies, including CMOS, FinFET, and FD-SOI, along with experience working across different process nodes.

EA License No: 13C6305

Reg. No.: R1874608 (Lee Jia Hou)

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