Senior Memory Design Engineer – Ultra-Low Power SRAM/IP

Ambiq; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Ambiq seeks an experienced Memory Design Engineer to work on embedded SRAM and RF IPs for ultra-low-power SoCs. You will contribute to SRAM compiler architectures, memory circuit design, and voltage-range optimization across conventional, near-threshold, and sub-threshold ranges.

The role requires collaboration with architecture, physical design, product engineering, foundry, EDA vendors, and silicon validation teams to deliver production-quality memory IP.

Qualifications

• Strong understanding of SRAM architecture, compiler design, and memory circuit design.
• Experience developing embedded SRAM or Register File IP for advanced FinFET tech.
• Scripting skills in Python, Tcl, or Perl for automation.

Responsibilities

• Design ultra-low power embedded SRAM and Register File IPs for advanced SoC products.
• Develop SRAM compiler architectures supporting multiple configurations and redundancy options.
• Design memory peripheral circuits: sense amps, write drivers, decoders, word-line drivers, pre-charge, and repair logic.

Skills

SRAM architecture

Compiler design

Memory circuit design

Python scripting

Cadence tools

SPICE simulations

Low-voltage SRAM

Memory IP delivery

Silicon bring-up

Debugging

Education

Bachelor’s/Master’s/PhD in Electrical Engineering

Tools

Cadence Virtuoso

HSPICE

Liberate MX

Job description

Ambiq seeks an experienced Memory Design Engineer to work on embedded SRAM and RF IPs for ultra-low-power SoCs. You will contribute to SRAM compiler architectures, memory circuit design, and voltage-range optimization across conventional, near-threshold, and sub-threshold ranges.

The role requires collaboration with architecture, physical design, product engineering, foundry, EDA vendors, and silicon validation teams to deliver production-quality memory IP.