Junior/Senior Memory Design Engineer (NVM) (Semiconductor)

talent trader group pte. ltd.; Singapore; On-site; SGD 70,000 - 120,000; Full time

Job summary

Talent Trader Group Pte. Ltd. seeks an experienced engineer to lead end-to-end circuit design for embedded NVM IP, covering conventional eFUSE/eFlash and future MRAM/RRAM technologies.

You will collaborate with layout teams, contribute to NVM DKs, Verilog models, datasheets, and test-chip validation efforts, leveraging Cadence Virtuoso and advanced EDA tools.

Qualifications

• Bachelor's or Master's degree in Microelectronics or related field.
• Minimum 3 years of hands-on experience in transistor-level analog and mixed-signal circuit design.
• Experience in at least one of the following memory technologies: eFUSE, eFlash, MRAM or RRAM.
• Strong proficiency with industry-standard analog EDA tools, including Cadence Virtuoso, Spectre, HSPICE, XA, FINESIM.

Responsibilities

• Develop architecture and execute end-to-end circuit design for embedded NVM IP.
• Collaborate with layout engineers in physical implementation of NVM memory arrays and analog peripheral circuits.
• Assist in development of NVM IP Design Kits (DK) including Verilog models, Liberty files, datasheets, bitmaps, and docs.
• Support design, implementation, and validation of NVM-related test chips.

Skills

Analog circuit design

Mixed-signal design

NVM knowledge

Education

Bachelor's or Master's in Microelectronics

Tools

Cadence Virtuoso

Spectre

HSPICE

XA

FINESIM

Job description

Job Description

• Develop architecture and execute end-to-end circuit design for embedded Non-Volatile Memory (NVM) IP, including conventional memory technologies such as eFUSE and eFlash, as well as next-generation memory solutions like MRAM and RRAM.
• Collaborate with and provide technical guidance to layout engineers in the physical implementation of NVM memory arrays and associated analog peripheral circuits.
• Assist in the development of NVM IP Design Kits (DK), including deliverables such as Verilog models, Liberty files, datasheets, bitmaps, and related documentation.
• Support the design, implementation, and validation of NVM-related test chips.

Requirements

• Bachelor's or Master's degree in Microelectronics or a related discipline.
• Minimum 3 years of hands-on experience in transistor-level analog and mixed-signal circuit design.
• Experience in at least one of the following memory technologies: eFUSE, eFlash, MRAM or RRAM.
• Strong proficiency with industry-standard analog EDA tools, including Cadence Virtuoso, Spectre, HSPICE, XA, FINESIM, and similar platforms for custom circuit design and simulation.
• Prior exposure to NVM chip testing and failure analysis is an advantage.
• Familiarity with advanced semiconductor process technologies, including CMOS, FinFET and FD-SOI, with experience designing across multiple process nodes.