IC Layout Engineer – Advanced Node Design & Automation

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; Presencial; SGD 90.000 - 140.000; Jornada completa

Descripción de la vacante

Broadcom Inc. in Singapore is seeking a skilled IC Layout Engineer to execute high-quality layouts for Standard Cells, I/O pads, and Mixed-Signal IP in advanced nodes.

You will manage layout schedules from transistor level to floorplanning, collaborate across sites, and use Cadence Virtuoso with Calibre for DRC/LVS/ERC analysis; knowledge of 5nm+ nodes and SKILL scripting is a plus. This position offers a challenging role in a global leader in semiconductors.

Formación

• Bachelor’s degree in Electronic Engineering.
• 3 to 4+ years of hands-on IC layout experience.

Responsabilidades

• Apply design guidelines and advanced rules to deliver high-performance layouts for Standard Cells, I/O pads and Mixed-Signal IP.
• Manage layout schedules from transistor level to cell- and block-level floorplanning.
• Adopt new layout methodologies to improve quality and efficiency.
• Communicate with engineers across sites to ensure alignment.
• Use Cadence Virtuoso to create and verify layouts.
• Perform DRC, LVS, ERC, Antenna, and EM/IR checks with Calibre.
• Apply ESD and latch-up knowledge for reliable I/O design.
• Understand deep sub-micron/nodes (5nm, 3nm, 2nm, 1.4nm) to optimize layout.
• Use Shell/Python/Tcl or Cadence SKILL to automate tasks.
• Work independently yet collaborate as a team player.

Conocimientos

IC layout

Cadence Virtuoso

Scripting (Shell/Python/Tcl/Cadence SK

Educación

Bachelor’s degree in Electronic Engineering

Herramientas

Cadence Virtuoso

Calibre

Shell scripting

Python

Tcl

Cadence SKILL

Descripción del empleo

Broadcom Inc. in Singapore is seeking a skilled IC Layout Engineer to execute high-quality layouts for Standard Cells, I/O pads, and Mixed-Signal IP in advanced nodes.

You will manage layout schedules from transistor level to floorplanning, collaborate across sites, and use Cadence Virtuoso with Calibre for DRC/LVS/ERC analysis; knowledge of 5nm+ nodes and SKILL scripting is a plus. This position offers a challenging role in a global leader in semiconductors.