Senior IC Layout Engineer, Optical AI Silicon

Lumilens Inc.; Singapore; On-site; SGD 120,000 - 160,000; Full time

Job summary

Lumilens Inc. is seeking a senior layout engineer in Singapore to lead floorplan and layout for high-speed analog and mixed-signal ICs, with photonic IC integration where needed.

You will own parasitic-aware design, impedance control, and successful tapeouts, collaborating with design teams in the US, India, and Singapore. The role requires expert Cadence Virtuoso, EM/IR drop expertise, PIC/layout PDK knowledge, and mentoring of the Singapore layout team.

Qualifications

• 8+ years in custom analog, RF, or high-speed mixed-signal IC layout with multiple tapeouts.
• Expert-level Cadence Virtuoso, including Layout XL and constraint-driven flows.
• Strong command of electromigration and IR drop fundamentals.
• Electromagnetics fundamentals for on-chip structures: inductors, transformers, transmission lines.
• Physical verification fluency: Calibre or PVS DRC/LVS, with parasitic extraction tools.

Responsibilities

• Own floorplan and layout for high-speed analog and mixed-signal blocks.
• Route high-speed signal paths with impedance control and EM structures.
• Finish chip assembly steps: pad ring, bump/pillar maps, density fill, and tape out.
• Drive parasitic-aware layout and iterate with designers on extraction.
• Own electromigration and IR drop closure, and sign-off on DRC/LVS/DFM/ESD.
• Support PIC layout and photonics integration when needed; mentor junior engineers.

Skills

Parasitic awareness

Electromagnetics fundamentals

Mentoring

Scripting (Python/SKILL)

Tapeout coordination

Layout leadership

Education

Bachelor's / Master's in Electrical/Electronic Engineering

Tools

Cadence Virtuoso

Calibre

PVS DRC/LVS

Job description

Lumilens Inc. is seeking a senior layout engineer in Singapore to lead floorplan and layout for high-speed analog and mixed-signal ICs, with photonic IC integration where needed.

You will own parasitic-aware design, impedance control, and successful tapeouts, collaborating with design teams in the US, India, and Singapore. The role requires expert Cadence Virtuoso, EM/IR drop expertise, PIC/layout PDK knowledge, and mentoring of the Singapore layout team.