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PERSOL Singapore is seeking an experienced engineer to lead multi‑die physical verification sign‑off for 3D IC packaging, including 3D_Stack, 3D_PERC and 3D_ANT flows, in a dynamic tape‑out environment. You will work closely with Package Design, ESD, and PV teams to resolve integration issues and drive flow automation.
The ideal candidate has a strong background in 3D IC design concepts, backend IC flow, and scripting proficiency, with excellent problem‑solving and communication skills.
Responsible for Multi-Dies Physical Verification Sign-off in area of (3D_Stack, 3D_PERC, 3D_ANT) for tape-out.
Co-work with Package Design Team to resolve multi-dies integration issues.
Co-work with ESD Team to run 3D_PERC flow.
Coordinates with Chip PV Team on active dies related issues (DRC, LVS, ANT, ERC, ESD)
Provide automation solutions to improve efficiency in tape-out flow.
Report on Tapeout PV issues.