Engineer/Staff Engineer – Multi-Dies Physical Verification Engineer

PERSOL; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

PERSOL Singapore Pte Ltd is seeking a Multi-Dies Physical Verification Specialist to own sign-off for tape-out in 3D IC areas (3D_Stack, 3D_PERC, 3D_ANT). You will collaborate with Package Design and ESD teams to resolve integration and flow issues, and drive automation to streamline tape-out PV processes.

The role requires strong scripting (Python/Tcl/Perl/C-shell), Calibre proficiency, and solid UNIX/Linux experience, plus excellent communication and analytical skills.

Qualifications

• Bachelor/Master’s degree in Electrical/Electronic Engineering / Computer Science.
• Familiar with 3D IC Design, like CoWoS, SoIC, EMIB etc.
• Familiar with IC Design front-to-backend flow
• Preferably well-versed in Calibre
• Proficient in script programming, such as Python, Tcl, Perl or C-shell
• Proficient in UNIX (Linux) platforms
• Strong communication skills, problem solving and analytical skills.

Responsibilities

• Perform multi-dies PV sign-off for tape-out (3D_Stack/3D_PERC/3D_ANT).
• Collaborate with Package Design Team to resolve integration issues.
• Co-work with ESD Team to run 3D_PERC flow.
• Coordinate with Chip PV Team on dies-related issues (DRC, LVS, ANT, ERC, ESD).
• Provide automation solutions to improve efficiency in tape-out flow.
• Report on Tapeout PV issues.

Skills

3D IC Design

Communication

Analytical skills

Problem solving

Education

Bachelor/Master's in Electrical/Electronic Engineering or CS

Tools

Calibre

Python

Tcl

Perl

C-shell

UNIX/Linux

Job description

Job Description:

• Responsible for Multi-Dies Physical Verification Sign-off in area of (3D_Stack, 3D_PERC, 3D_ANT) for tape-out.
• Co-work with Package Design Team to resolve multi-dies integration issues.
• Co-work with ESD Team to run 3D_PERC flow.
• Coordinates with Chip PV Team on active dies related issues (DRC, LVS, ANT, ERC, ESD)
• Provide automation solutions to improve efficiency in tape-out flow.
• Report on Tapeout PV issues.

Requirements:

• Bachelor/Master’s Degree in Electrical/Electronic Engineering / Computer Science
• Familiar with 3D IC Design, like CoWoS, SoIC, EMIB etc.
• Familiar with IC Design front-to-backend flow
• Preferably well-versed in Calibre
• Proficient in script programming, such as Python, Tcl, Perl or C-shell
• Proficient in UNIX (Linux) platforms
• Strong communication skills, problem solving and analytical skills.

PERSOL Singapore Pte Ltd • UEN No. 200007268E • EA License No. 01C4394 • EA Registration No. R22111378 (Ong Xin Yee)

By sending us your personal data and curriculum vitae (CV), you are deemed to consent to PERSOL Singapore Pte Ltd and its affiliates to collect, use and disclose your personal data for the purposes set out in the Privacy Policy available at https://www.persolsingapore.com/policies. You acknowledge that you have read, understood, and agree with the Privacy Policy.