Design Verification Manager

ovt; Singapore; On-site; SGD 180,000 - 320,000; Full time

Job summary

ovt in Singapore seeks a Design Verification Manager to lead a high-performance verification team. You will drive advanced verification strategies across complex SoC designs, including UVM-based workflows, C/C++ co-simulation, and mixed-mode simulation, to ensure robust quality.

Ideal candidates have 10+ years in ASIC/SoC verification, strong leadership and excellent communication. This role emphasizes disciplined execution, early risk detection, and continuous process improvement within a

Qualifications

• At least 10 years of relevant experience in ASIC/SoC verification.
• Proven expertise in UVM and system-level verification.
• Experience with EDA tools and ASIC development flows.
• Excellent leadership, discipline and communication.

Responsibilities

• Be in-charge of a passionate verification team that is constantly pushing the limits.
• Develop and deploy state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification.
• Conduct thorough test plan reviews systematically, and execute the plan on-time with high quality.
• Achieve zero-defects with the best and smartest approach to the large verification space.

Skills

UVM verification methodology

Team leadership

Communication skills

SoC verification

Test plan development

C programming

Python & Perl scripting

Education

MSEE/BSEE in Electrical Engineering or Computer Engineering

Tools

RTL design

EDA tools

Job description

As a Design Verification Manager, you are expected to carry out the following responsibilities.

• Be in-charge of a passionate verification team that is constantly pushing the limits
• Develop and deploy state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification
• Conduct thorough test plan reviews systematically, and execute the plan on-time with high quality
• Achieve zero-defects with the best and smartest approach to the large verification space.

Requirements

• Strong knowledge of SoC design principles, including IP block integration and system-level verification
• Experience with test plan development, execution, and analysis
• Familiarity with EDA tools and development flows for ASIC verification
• Highly disciplined, quality-minded, and highly driven for excellence.
• Excellent team leader and good communication skills.
• Strong expertise in UVM verification methodology.
• Experience in C and/or a scripting language such as python or perl.
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with at least 10 years of relevant experience.
• Experience in RTL design is a plus.
• Experience in video processing and video analytics is a plus.
• Passionate and strong in general programming is a plus.