Senior SerDes Verification Engineer | UVM, PCIe/UCIe

Advanced Micro Devices, Inc.; Singapore; On-site; SGD 90,000 - 130,000; Full time

Benefits offered by this job

AMD benefits

Job summary

Advanced Micro Devices, Inc. seeks a SerDes Verification Engineer in Singapore to verify high‑speed SerDes interfaces, test signal integrity, and ensure protocol compliance. You will collaborate with hardware and design teams across sites to resolve issues and validate performance.

The role requires hands-on verification using UVM/SystemVerilog, knowledge of PCIe/UCIe, and strong debugging skills. You will develop automated tests and contribute to design verification improvements.

Qualifications

• Bachelor's or Master’s degree in Electrical/Computer Engineering or related field.
• Experience in SerDes verification or high-speed communication verification.
• Strong knowledge of HDL verification methodologies and protocols.

Responsibilities

• Verification of SerDes designs: develop and execute verification plans and testbenches for SerDes IPs and subsystems.
• Drive formal verification for the block and write formal properties and assertions.
• Estimate time to write new feature tests and test environment changes.
• Build directed and random verification tests and review coverage metrics.
• Design and implement verification testbenches using UVM/SystemVerilog/VHDL.
• Perform simulations, analyze results, and debug timing/protocol issues.
• Evaluate performance characteristics: jitter, BER, signal integrity, eye diagrams.
• Verify adherence to protocols like UCIe, PCIe, Ethernet, USB, DDR, DisplayPort or custom protocols.
• Develop automated regression tests for robustness across versions.
• Collaborate with design, hardware, and software teams; document results.

Skills

SerDes verification

UVM/SystemVerilog

Signal integrity analysis

Debugging

Team collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

UVM

SystemVerilog

VHDL

Python

Job description

Advanced Micro Devices, Inc. seeks a SerDes Verification Engineer in Singapore to verify high‑speed SerDes interfaces, test signal integrity, and ensure protocol compliance. You will collaborate with hardware and design teams across sites to resolve issues and validate performance.

The role requires hands-on verification using UVM/SystemVerilog, knowledge of PCIe/UCIe, and strong debugging skills. You will develop automated tests and contribute to design verification improvements.