Digital IC Design Engineer (SoC Timing)

Realtek Singapore Private Limited; Singapore; On-site; SGD 90,000 - 140,000; Full time

Job summary

Realtek Singapore Private Limited in Singapore is seeking a timing-driven ASIC engineer to work with system engineers on timing requirements, synthesis and timing closure.

You will gain experience in power structure, DFT, and UNIX/Linux scripting, with emphasis on ASIC design flow and verification for release.

The role requires a bachelor’s or master’s degree in electronic engineering and strong communication skills, with hands-on experience in logic synthesis and STA.

Qualifications

• Bachelor’s or master’s degree in electronic engineering with ASIC design experience.
• Familiar with ASIC design flow.
• Experience in logic synthesis, static timing analysis, timing closure.
• Good understanding of DFT and Power structure.
• Familiar with UNIX/ Linux environment and scripting.
• Good communication and interpersonal skills.

Responsibilities

• Work with system engineers on timing requirements and feedback on optimization.
• Work on SoC timing constraint, synthesis and timing closure.
• Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains.
• Conduct formal verification for release comparison.
• Support back-end implementation on timing violation analysis and fix.
• Support scan insertion and optimization.
• Support on power structure and power optimization.

Skills

Logic synthesis

Static timing analysis

Timing closure

DFT

Power structure

UNIX/Linux scripting

Communication skills

Education

Bachelor’s or Master’s degree in electronic engineering

Job description

JOB DESCRIPTION

• Work with system engineers on timing requirements and feedback on optimization.

• Work on SoC timing constraint, synthesis and timing closure.

• Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains.

• Conduct formal verification for release comparison.

• Support back-end implementation on timing violation analysis and fix.

• Support scan insertion and optimization.

• Support on power structure and power optimization.

JOB REQUIREMENTS

• Bachelor’s or master’s degree in electronic engineering with ASIC design experience.

• Familiar with ASIC design flow.

• Experience in logic synthesis, static timing analysis, timing closure.

• Good understanding of DFT and Power structure.

• Familiar with UNIX/ Linux environment and scripting.

• Good communication and interpersonal skills.