Principal IC Design Engineer - Automotive AI Silicon

Search Staffing Pte Ltd; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Unknown Automotive Tech Singapore is seeking a Principal / Senior IC Design Engineer to drive digital IP and SoC blocks from concept through silicon. You will own micro-architecture, write RTL, and work across the full ASIC design flow in a collaborative, global team.

The role requires strong Verilog/SystemVerilog skills, TCL/Python scripting, and hands-on timing and synthesis experience. Pre/post-silicon bring-up, clear documentation, and a proactive problem-solving approach are essential.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronic Engineering or related field.
• Proven experience across the ASIC design flow and methodologies.
• Strong RTL coding skills in Verilog or SystemVerilog.
• Hands-on experience with synthesis, timing, and scripting (TCL/Python).
• Exposure to low-power techniques and power integrity is a plus.
• Familiarity with industry EDA tools from major vendors.

Responsibilities

• Take digital IP and SoC blocks from concept to silicon.
• Own micro-architecture and RTL implementation for ASIC designs.
• Write synthesizable RTL in Verilog/SystemVerilog for IPs and SoCs.
• Run linting, CDC checks, and low-power verification (UPF/CPF).
• Handle logic synthesis, timing constraints, and timing closure.
• Collaborate with verification for test plans and quality.
• Support pre-silicon validation and post-silicon bring-up and debug.
• Produce clear technical documentation throughout the design cycle.

Skills

Verilog

SystemVerilog

ASIC flow

TCL scripting

Python

EDA tools

Power integrity

Team collaboration

Education

Bachelor's or Master's in Electrical/Electronic Eng

Tools

Synopsys

Cadence

Siemens

Job description

Unknown Automotive Tech Singapore is seeking a Principal / Senior IC Design Engineer to drive digital IP and SoC blocks from concept through silicon. You will own micro-architecture, write RTL, and work across the full ASIC design flow in a collaborative, global team.

The role requires strong Verilog/SystemVerilog skills, TCL/Python scripting, and hands-on timing and synthesis experience. Pre/post-silicon bring-up, clear documentation, and a proactive problem-solving approach are essential.