Senior ASIC Verification Engineer - SystemVerilog/UVM Expert

ESSIQ AB; Malmö kommun; On-site; SEK 900,000 - 1,200,000; Full time

Benefits offered by this job

Pension contributions

Comprehensive insurance coverage

Attractive employee benefits

Job summary

ESSIQ AB in Malmö seeks an experienced Senior ASIC Verification Engineer to join our international R&D team. You will develop advanced ASIC/SoC verification environments, build testbenches from scratch, and develop VIPs and SVA to ensure high-quality designs.

The role offers collaboration across disciplines and opportunities to influence verification methodologies. You will work in a globally connected environment where delivering robust verification solutions is critical for next‑generation

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.
• At least five years of relevant ASIC/SoC verification experience.
• Excellent knowledge of SystemVerilog and UVM.
• Proven hands-on experience developing verification testbenches from scratch.
• Experience developing and integrating Verification IPs (VIPs).
• Good understanding of assertions, functional and code coverage, and coverage-driven verification.
• Solid understanding of digital design and modern verification methodologies.
• Experience working in Linux-based development environments.
• Strong communication and collaboration in international teams.

Responsibilities

• Developing advanced ASIC and SoC verification environments using SystemVerilog and UVM.
• Designing and implementing testbenches from scratch, including drivers, monitors, scoreboards, and sequences.
• Developing, integrating, and maintaining Verification IPs (VIPs).
• Implementing SystemVerilog Assertions (SVA) to ensure robust design verification.
• Developing functional and code coverage strategies, identifying verification gaps, and driving coverage closure.
• Maintaining and improving existing test environments as designs evolve.
• Collaborating with experienced engineers and multidisciplinary teams in an international development environment.
• Contributing to verification methodologies, best practices, and continuous improvements.

Skills

SystemVerilog

UVM

Testbenches

VIPs

Assertions

Linux

Education

Bachelor's or Master's in Electrical/Computer Eng.

Tools

CI environments

Job description

ESSIQ AB in Malmö seeks an experienced Senior ASIC Verification Engineer to join our international R&D team. You will develop advanced ASIC/SoC verification environments, build testbenches from scratch, and develop VIPs and SVA to ensure high-quality designs.

The role offers collaboration across disciplines and opportunities to influence verification methodologies. You will work in a globally connected environment where delivering robust verification solutions is critical for next‑generation