Senior ASIC Verification Engineer

Swediumglobal; Lund, Stockholm; On-site; SEK 670,390 - 893,854; Full time

Job summary

A technology solutions provider is seeking an experienced ASIC Verification Engineer in Lund, Sweden. The role involves developing verification plans, enhancing verification environments, and driving testing strategies. A Master's degree in a related field and extensive ASIC verification experience are required. Candidates should possess strong collaboration and creative problem-solving skills. This position offers a dynamic work environment focused on continuous improvement.

Qualifications

• 7 years of verification experience in ASIC or FPGA at IP, sub-system, and chip levels.
• Hands-on experience with designing UVM test environments.
• Willingness to learn and apply new knowledge daily.

Responsibilities

• Develop comprehensive verification plans with specifications.
• Architect and enhance verification environments.
• Implement and maintain UVCs for thorough design verification.

Skills

ASIC Verification

UVM Test Environments

Creative Problem-Solving

Collaboration

Communication Skills

Education

Master’s degree in Electrical Engineering, Computer Engineering, or related field

Job description

SwediumGlobal is seeking an ASIC Verification Engineer

Location: Lund, Sweden

Role:

We are looking for an experienced verification engineer.

What the candidate will do:

1. Develop comprehensive verification plans, including specifications.
2. Architect and enhance state-of-the-art verification environments.
3. Implement and maintain UVCs, ensuring thorough verification of the design.
4. Drive random and directed testing strategies to uncover bugs.
5. Leverage advanced coverage techniques to ensure verification completeness.
6. Champion continuous improvement in product quality, efficiency, and workflows.

Qualifications:

• A Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Expertise in ASIC or FPGA verification at IP, sub-system, and chip levels, using SystemVerilog UVM; possibly 7 years of verification experience.
• Hands-on experience designing UVM test environments and driving coverage closure.
• Curiosity and willingness to learn and apply new knowledge daily.
• Creative problem-solving skills and innovative mindset.
• Strong collaboration and communication skills, with the ability to work independently.
• Results-oriented with a passion for continuous improvement and faster solutions.

Job Overview

• Location: Kista, Sweden
• Vacancy: 1