ASIC verification Engineer

Swediumglobal; Göteborgs kommun; On-site; SEK 646,412 - 861,883; Full time

Job summary

A growing System Engineering company is looking for an experienced ASIC Verification Engineer in Gothenburg, Sweden. The ideal candidate should possess over 10 years of ASIC verification experience and have a solid knowledge of UVM and System Verilog. Responsibilities include defining verification strategies, implementing test cases, and collaborating with development teams. This role offers a chance to guide early career engineers in a dynamic work environment.

Qualifications

• Over 10 years of experience in ASIC verification.
• Hands-on experience in IP Verification.
• Strong knowledge in UVM methodology and System Verilog.

Responsibilities

• Define verification requirements and strategies for ASIC designs.
• Implement verification environments and test cases.
• Collaborate with development teams to understand product requirements.

Skills

ASIC verification

UVM

System Verilog

English communication

Education

Master’s degree in electrical or computer engineering

Job description

Swedium Global Servicesis the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.

Assignment Description

Location - onsite, Sweden

Job Title -ASIC verification Engineer

Role Overview

What you will do

• Define verification requirements and strategies for ASIC designs based on functional specifications and following Ericsson development processes
• Implement verification environments and test cases to complete verification plans
• Measure functional and code coverage metrics, and drive toward completion targets
• Debug RTL in conjunction with designers
• Collaborate with other development teams to understand overall product requirements and drive efficient solutions
• Contribute to the continuous improvement of products, tools, and processes
• Guide and educate early career engineers

You will bring

• 10+ years of experience in ASIC verification
• Good hands-on exposure on IP Verification and strong in UVM, System Verilog
• Master’s degree in electrical or computer engineering or equivalent
• Excellent knowledge of UVM methodology and System Verilog
• An analytical approach and be results oriented with the ability to deliver under pressure
• Excellent English verbal and written communication skills
• High self-motivation, an ability to work independently while being a great teammate.