ASIC verification Engineer

Swediumglobal; Lunds kommun; On-site; SEK 558,000 - 781,200; Full time

Job summary

A leading system engineering firm in Sweden is seeking an experienced ASIC Verification Engineer. You will define verification strategies, implement test cases, and collaborate with development teams. The ideal candidate has over 5 years of experience in ASIC verification, a Master's degree in a related field, and excellent knowledge of UVM methodology. This role is onsite in Sweden.

Qualifications

• 5+ years of experience in ASIC verification.
• Excellent knowledge of UVM methodology and System Verilog.
• Experience in formal verification required.

Responsibilities

• Define verification requirements and strategies for ASIC designs.
• Implement verification environments and test cases.
• Measure functional and code coverage metrics.

Skills

ASIC verification

UVM methodology

System Verilog

Analytical skills

Excellent communication

Education

Master’s degree in Electrical or Computer Engineering or equivalent

Tools

C

Emulation

HLS

Job description

Swedium Global Services is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.

Job Name-ASIC verification Engineer

Location-Onsite in Sweden

What you will do

• Define verification requirements and strategies for ASIC designs based on functional specifications and following Ericsson development processes
• Implement verification environments and test cases to complete verification plans
• Measure functional and code coverage metrics, and drive toward completion targets
• Debug RTL in conjunction with designers
• Collaborate with other development teams to understand overall product requirements and drive efficient solutions
• Contribute to the continuous improvement of products, tools, and processes
• Guide and educate early career engineers

You will bring

• 5+ years of experience in ASIC verification
• Master’s degree in Electrical or Computer Engineering or equivalent
• Excellent knowledge of UVM methodology and System Verilog
• Experiences in Formal verification
• Knowledge of C, Emulation & HLS is preferable
• An analytical approach and be results oriented with the ability to deliver under pressure
• Excellent English verbal and written communication skills
• High self-motivation, an ability to work independently while being a great teammate.