ML-Powered Evidence Ranking for ASIC Verification & Debug

Ericsson; Stockholms kommun; On-site; SEK 201,000 - 268,000; Part time

Benefits offered by this job

Mentorship from Ericsson verification

Access to real tools and data

Job summary

Ericsson in Sweden is offering a master’s thesis opportunity focusing on learned evidence ranking for failure diagnosis and automated testbench quality assessment in ASIC verification. You will work with real production regression data from Ericsson's environment, bridging hardware verification and machine learning, under mentorship from Ericsson engineers.

The project spans data understanding, problem framing, model building and evaluation, with potential to extend to auditable scoring and

Qualifications

• Master’s student in electrical or computer engineering, computer science, embedded systems, or a similar field.
• Knowledge of computer architecture, ASIC design and RTL/HDL coding.
• Experience with SystemVerilog and testbench design; working knowledge of UVM is preferred.
• Scripting experience, preferably Tcl or Python, for EDA tools.
• Fundamentals of artificial intelligence and machine learning.
• Exposure to at least one AI/ML model architecture, from data preparation through evaluation.
• An analytical and research-oriented mindset.
• Interest in verification, observability and data-driven engineering.

Responsibilities

• Build a data-driven framework for automated failure diagnosis and testbench quality assessment.
• Capture and correlate relevant verification events beyond conventional UVM messages.
• Train and evaluate a model that ranks events by diagnostic relevance.
• Compare the results with expert engineer assessments and manual triage effort, using real production regression data from an Ericsson accelerator IP.
• Develop a prototype for auditable testbench quality scoring.
• Stretch goal (optional): explore whether failure patterns can be detected before an error appears.

Skills

Computer architecture

ASIC design

RTL/HDL coding

SystemVerilog

UVM

Scripting (Python, Tcl)

AI/ML fundamentals

ML model architectures

Analytical mindset

Verification observability

Education

Master’s student in electrical or computer engineering, computer science, embedded systems, or a similar field

Tools

UVM

SystemVerilog

Job description

Ericsson in Sweden is offering a master’s thesis opportunity focusing on learned evidence ranking for failure diagnosis and automated testbench quality assessment in ASIC verification. You will work with real production regression data from Ericsson's environment, bridging hardware verification and machine learning, under mentorship from Ericsson engineers.

The project spans data understanding, problem framing, model building and evaluation, with potential to extend to auditable scoring and