Senior ASIC Synthesis & PPA Engineer: Power, Timing, QoR

Ericsson; Stockholms kommun; On-site; SEK 900,000 - 1,200,000; Full time

Job summary

Ericsson Sweden is seeking an experienced ASIC Synthesis & PPA Engineer to own physical-aware synthesis, floorplan-driven netlist optimization and QoR closure across RTL and PPA. You will work closely with RTL design, integration, architecture, place-and-route, and DFT teams throughout the full design cycle.

You will drive timing analysis across PVT corners, validate UPF/CPF power intent, and collaborate on early floorplan exploration, area optimization, and PPA trade-offs.

Qualifications

• 8+ years of experience in physical synthesis or logic design implementation.
• Expert-level experience with Synopsys/Cadence EDA tools.
• Strong TCL; Python scripting skills.
• Experience in low power design strategies.
• Experience in analyzing PPA results and providing RTL-level recommendations.
• Multiple tape-outs on advanced nodes (7nm or below).

Responsibilities

• Execute physical-aware and floorplan-driven synthesis flows to reduce post-layout timing and congestion risks.
• Identify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming.
• Drive QoR closure by tracking metrics across design iterations and process corners.
• Work on PPA optimization and structured design space exploration.
• Run block-level and full-chip STA for timing analysis across PVT corners; support MMMC timing closure.
• Validate UPF/CPF power intent implementation, including isolation cells and level shifters.
• Collaborate with RTL, physical design, and silicon teams on floorplan exploration and PPA trade-offs.
• Apply AI-assisted tools for log analysis and QoR comparison, while validating results.

Skills

Physical synthesis

RTL design

SDC constraints

TCL scripting

Python scripting

Low power design

QoR optimization

Timing analysis

Tools

Synopsys EDA tools

Cadence EDA tools

Job description

Ericsson Sweden is seeking an experienced ASIC Synthesis & PPA Engineer to own physical-aware synthesis, floorplan-driven netlist optimization and QoR closure across RTL and PPA. You will work closely with RTL design, integration, architecture, place-and-route, and DFT teams throughout the full design cycle.

You will drive timing analysis across PVT corners, validate UPF/CPF power intent, and collaborate on early floorplan exploration, area optimization, and PPA trade-offs.